156 lines
3.7 KiB
C
156 lines
3.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C546/82C547 & 82C596/82C597 chipsets.
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* Authors: plant/nerd73
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 plant/nerd73.
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct
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{
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uint8_t idx,
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regs[16];
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port_92_t *port_92;
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} opti5x7_t;
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static void
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opti5x7_recalc(opti5x7_t *dev)
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{
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uint32_t base;
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uint32_t i, j, shflags = 0;
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uint32_t reg, lowest_bit;
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uint32_t write = 0;
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for (i = 0; i < 8; i++) {
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j = i / 2.01; /*Probably not a great way of doing this, but it does work*/
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base = 0xc0000 + (j << 14);
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lowest_bit = j * 2;
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reg = 0x04 + ((base >> 16) & 0x01);
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shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[0x06] & 0x01) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xe0000, 0x10000, shflags);
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shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : write;
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write = (dev->regs[0x06] & 0x04) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xf0000, 0x10000, shflags);
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flushmmucache();
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}
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static void
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opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti5x7_t *dev = (opti5x7_t *) priv;
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pclog("Write %02x to OPTi 5x7 address %02x\n", val, addr);
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switch (addr) {
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case 0x22:
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dev->idx = val;
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break;
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case 0x24:
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dev->regs[dev->idx] = val;
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switch(dev->idx) {
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case 0x02:
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08);
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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opti5x7_recalc(dev);
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break;
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}
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break;
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}
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}
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static uint8_t
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opti5x7_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti5x7_t *dev = (opti5x7_t *) priv;
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switch (addr) {
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case 0x24:
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pclog("Read from OPTi 5x7 register %02x\n", dev->idx);
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ret = dev->regs[dev->idx];
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break;
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}
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return ret;
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}
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static void
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opti5x7_close(void *priv)
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{
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opti5x7_t *dev = (opti5x7_t *) priv;
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free(dev);
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}
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static void *
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opti5x7_init(const device_t *info)
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{
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opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t));
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memset(dev, 0, sizeof(opti5x7_t));
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io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
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dev->port_92 = device_add(&port_92_device);
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// pclog("OPTi 5x7 init\n");
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opti5x7_recalc(dev);
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return dev;
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}
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const device_t opti5x7_device = {
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"OPTi 82C5x6/82C5x7",
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0,
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0,
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opti5x7_init, opti5x7_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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