1276 lines
35 KiB
C
1276 lines
35 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel 8253/8254 Programmable Interval
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* Timer.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2019 Miran Grca.
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*/
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#include <inttypes.h>
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#include <math.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/device.h>
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#include <86box/timer.h>
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#include <86box/cassette.h>
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#include <86box/dma.h>
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#include <86box/io.h>
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#include <86box/nmi.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/pit_fast.h>
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#include <86box/ppi.h>
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#include <86box/machine.h>
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#include <86box/sound.h>
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#include <86box/snd_speaker.h>
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#include <86box/video.h>
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#include <86box/plat_unused.h>
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pit_intf_t pit_devs[2];
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double cpuclock;
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double PITCONSTD;
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double PAS16CONSTD;
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double PAS16CONST2D;
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double PASSCSICONSTD;
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double SYSCLK;
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double isa_timing;
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double bus_timing;
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double pci_timing;
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double agp_timing;
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double PCICLK;
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double AGPCLK;
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uint64_t PITCONST;
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uint64_t PAS16CONST;
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uint64_t PAS16CONST2;
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uint64_t PASSCSICONST;
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uint64_t ISACONST;
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uint64_t CGACONST;
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uint64_t MDACONST;
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uint64_t HERCCONST;
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uint64_t VGACONST1;
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uint64_t VGACONST2;
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uint64_t RTCCONST;
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uint64_t ACPICONST;
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int refresh_at_enable = 1;
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int io_delay = 5;
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int64_t firsttime = 1;
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#define PIT_PS2 16 /* The PIT is the PS/2's second PIT. */
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#define PIT_EXT_IO 32 /* The PIT has externally specified port I/O. */
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#define PIT_CUSTOM_CLOCK 64 /* The PIT uses custom clock inputs provided by another provider. */
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#define PIT_SECONDARY 128 /* The PIT is secondary (ports 0048-004B). */
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#ifdef ENABLE_PIT_LOG
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int pit_do_log = ENABLE_PIT_LOG;
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static void
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pit_log(const char *fmt, ...)
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{
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va_list ap;
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if (pit_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define pit_log(fmt, ...)
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#endif
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static void
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ctr_set_out(ctr_t *ctr, int out, void *priv)
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{
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pit_t *pit = (pit_t *)priv;
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if (ctr == NULL)
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return;
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if (ctr->out_func != NULL)
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ctr->out_func(out, ctr->out, pit);
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ctr->out = out;
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}
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static void
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ctr_decrease_count(ctr_t *ctr)
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{
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if (ctr->bcd) {
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ctr->units--;
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if (ctr->units == -1) {
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ctr->units = -7;
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ctr->tens--;
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if (ctr->tens == -1) {
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ctr->tens = -7;
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ctr->hundreds--;
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if (ctr->hundreds == -1) {
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ctr->hundreds = -7;
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ctr->thousands--;
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if (ctr->thousands == -1) {
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ctr->thousands = -7;
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ctr->myriads--;
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if (ctr->myriads == -1)
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ctr->myriads = -7; /* 0 - 1 should wrap around to 9999. */
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}
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}
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}
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}
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} else
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ctr->count = (ctr->count - 1) & 0xffff;
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}
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static void
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ctr_load_count(ctr_t *ctr)
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{
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int l = ctr->l ? ctr->l : 0x10000;
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ctr->count = l;
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pit_log("ctr->count = %i\n", l);
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ctr->null_count = 0;
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ctr->newcount = !!(l & 1);
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/* Undocumented feature - writing MSB after reload after writing LSB causes an instant reload. */
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ctr->incomplete = !!(ctr->wm & 0x80);
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}
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static void
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ctr_tick(ctr_t *ctr, void *priv)
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{
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pit_t *pit = (pit_t *)priv;
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uint8_t state = ctr->state;
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if ((state & 0x03) == 0x01) {
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/* This is true for all modes */
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ctr_load_count(ctr);
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ctr->state++;
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if (((ctr->m & 0x07) == 0x01) && (ctr->state == 2))
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ctr_set_out(ctr, 0, pit);
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} else switch (ctr->m & 0x07) {
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case 0:
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/* Interrupt on terminal count */
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switch (state) {
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case 2:
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if (ctr->gate && (ctr->count >= 1)) {
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ctr_decrease_count(ctr);
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if (ctr->count < 1) {
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ctr->state = 3;
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ctr_set_out(ctr, 1, pit);
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}
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}
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break;
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case 3:
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ctr_decrease_count(ctr);
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break;
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default:
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break;
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}
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break;
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case 1:
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/* Hardware retriggerable one-shot */
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switch (state) {
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case 2:
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if (ctr->count >= 1) {
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ctr_decrease_count(ctr);
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if (ctr->count < 1) {
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ctr->state = 3;
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ctr_set_out(ctr, 1, pit);
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}
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}
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break;
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case 3:
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case 6:
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ctr_decrease_count(ctr);
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break;
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default:
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break;
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}
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break;
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case 2:
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case 6:
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/* Rate generator */
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switch (state) {
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case 3:
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ctr_load_count(ctr);
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ctr->state = 2;
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ctr_set_out(ctr, 1, pit);
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break;
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case 2:
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if (ctr->gate == 0)
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break;
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else if (ctr->count >= 2) {
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ctr_decrease_count(ctr);
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if (ctr->count < 2) {
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ctr->state = 3;
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ctr_set_out(ctr, 0, pit);
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}
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}
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break;
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default:
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break;
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}
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break;
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case 3:
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case 7:
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/* Square wave mode */
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switch (state) {
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case 2:
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if (ctr->gate == 0)
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break;
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else if (ctr->count >= 0) {
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if (ctr->bcd) {
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ctr_decrease_count(ctr);
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if (!ctr->newcount)
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ctr_decrease_count(ctr);
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} else
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ctr->count -= (ctr->newcount ? 1 : 2);
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if (ctr->count == 0) {
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ctr_set_out(ctr, 0, pit);
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ctr_load_count(ctr);
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ctr->state = 3;
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} else if (ctr->newcount)
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ctr->newcount = 0;
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}
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break;
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case 3:
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if (ctr->gate == 0)
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break;
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else if (ctr->count >= 0) {
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if (ctr->bcd) {
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ctr_decrease_count(ctr);
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ctr_decrease_count(ctr);
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if (ctr->newcount)
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ctr_decrease_count(ctr);
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} else
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ctr->count -= (ctr->newcount ? 3 : 2);
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if (ctr->count == 0) {
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ctr_set_out(ctr, 1, pit);
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ctr_load_count(ctr);
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ctr->state = 2;
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} else if (ctr->newcount)
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ctr->newcount = 0;
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}
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break;
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default:
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break;
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}
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break;
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case 4:
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case 5:
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/* Software triggered strobe */
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/* Hardware triggered strobe */
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if ((ctr->gate != 0) || (ctr->m != 4)) {
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switch (state) {
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case 0:
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case 6:
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ctr_decrease_count(ctr);
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break;
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case 2:
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if (ctr->count >= 1) {
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ctr_decrease_count(ctr);
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if (ctr->count < 1) {
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ctr->state = 3;
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ctr_set_out(ctr, 0, pit);
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}
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}
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break;
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case 3:
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ctr->state = 0;
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ctr_set_out(ctr, 1, pit);
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break;
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default:
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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void
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ctr_clock(void *data, int counter_id)
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{
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pit_t *pit = (pit_t *) data;
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ctr_t *ctr = &pit->counters[counter_id];
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/* FIXME: Is this even needed? */
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if ((ctr->state == 3) && (ctr->m != 2) && (ctr->m != 3))
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return;
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if (ctr->using_timer)
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return;
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ctr_tick(ctr, pit);
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}
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static void
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ctr_set_state_1(ctr_t *ctr)
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{
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uint8_t mode = (ctr->m & 0x03);
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int do_reload = !!ctr->incomplete || (mode == 0) || (ctr->state == 0);
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ctr->incomplete = 0;
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if (do_reload)
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ctr->state = 1 + ((mode == 1) << 2);
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}
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static void
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ctr_load(ctr_t *ctr)
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{
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if (ctr->l == 1) {
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/* Count of 1 is illegal in modes 2 and 3. What happens here was
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determined experimentally. */
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if (ctr->m == 2)
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ctr->l = 2;
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else if (ctr->m == 3)
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ctr->l = 0;
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}
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if (ctr->using_timer)
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ctr->latch = 1;
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else
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ctr_set_state_1(ctr);
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if (ctr->load_func != NULL) {
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uint32_t count = ctr->l ? ctr->l : 0x10000;
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if (ctr->bcd) {
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uint32_t bcd_count = (((count >> 16) & 0xf) * 10000) |
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(((count >> 12) & 0xf) * 1000 ) |
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(((count >> 8 ) & 0xf) * 100 ) |
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(((count >> 4 ) & 0xf) * 10 ) |
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(count & 0xf);
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ctr->load_func(ctr->m, bcd_count);
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} else
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ctr->load_func(ctr->m, ctr->l ? ctr->l : 0x10000);
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}
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pit_log("Counter loaded, state = %i, gate = %i, latch = %i\n", ctr->state, ctr->gate, ctr->latch);
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}
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static __inline void
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ctr_latch_status(ctr_t *ctr)
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{
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ctr->read_status = (ctr->ctrl & 0x3f) | (ctr->out ? 0x80 : 0) | (ctr->null_count ? 0x40 : 0);
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ctr->do_read_status = 1;
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}
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static __inline void
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ctr_latch_count(ctr_t *ctr)
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{
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int count = (ctr->latch || (ctr->state == 1)) ? ctr->l : ctr->count;
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switch (ctr->rm & 0x03) {
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case 0x00:
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/* This should never happen. */
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break;
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case 0x01:
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/* Latch bits 0-7 only. */
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ctr->rl = ((count << 8) & 0xff00) | (count & 0xff);
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ctr->latched = 1;
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break;
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case 0x02:
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/* Latch bit 8-15 only. */
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ctr->rl = (count & 0xff00) | ((count >> 8) & 0xff);
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ctr->latched = 1;
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break;
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case 0x03:
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/* Latch all 16 bits. */
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ctr->rl = count;
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ctr->latched = 2;
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break;
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default:
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break;
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}
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pit_log("rm = %x, latched counter = %04X\n", ctr->rm & 0x03, ctr->rl & 0xffff);
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}
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uint16_t
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pit_ctr_get_count(void *data, int counter_id)
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{
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const pit_t *pit = (pit_t *) data;
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const ctr_t *ctr = &pit->counters[counter_id];
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return (uint16_t) ctr->l;
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}
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void
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pit_ctr_set_load_func(void *data, int counter_id, void (*func)(uint8_t new_m, int new_count))
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{
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if (data == NULL)
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return;
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pit_t *pit = (pit_t *) data;
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ctr_t *ctr = &pit->counters[counter_id];
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ctr->load_func = func;
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}
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void
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pit_ctr_set_out_func(void *data, int counter_id, void (*func)(int new_out, int old_out, void *priv))
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{
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if (data == NULL)
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return;
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pit_t *pit = (pit_t *) data;
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ctr_t *ctr = &pit->counters[counter_id];
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ctr->out_func = func;
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}
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void
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pit_ctr_set_gate(void *data, int counter_id, int gate)
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{
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pit_t *pit = (pit_t *) data;
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ctr_t *ctr = &pit->counters[counter_id];
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int old = ctr->gate;
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uint8_t mode = ctr->m & 3;
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switch (mode) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 6:
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case 7:
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if (!old && gate) {
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/* Here we handle the rising edges. */
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if (mode & 1) {
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if (mode != 1)
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ctr_set_out(ctr, 1, pit);
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ctr->state = 1;
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} else if (mode == 2)
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ctr->state = 3;
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} else if (old && !gate) {
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/* Here we handle the lowering edges. */
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if (mode & 2)
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ctr_set_out(ctr, 1, pit);
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}
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break;
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default:
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break;
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}
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ctr->gate = gate;
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}
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static __inline void
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pit_ctr_set_clock_common(ctr_t *ctr, int clock, void *priv)
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{
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pit_t *pit = (pit_t *)priv;
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int old = ctr->clock;
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ctr->clock = clock;
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if (ctr->using_timer && ctr->latch) {
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if (old && !ctr->clock) {
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ctr_set_state_1(ctr);
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ctr->latch = 0;
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}
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} else if (ctr->using_timer && !ctr->latch) {
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if (ctr->state == 1) {
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if (!old && ctr->clock)
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ctr->s1_det = 1; /* Rising edge. */
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else if (old && !ctr->clock) {
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ctr->s1_det++; /* Falling edge. */
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if (ctr->s1_det >= 2) {
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ctr->s1_det = 0;
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ctr_tick(ctr, pit);
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}
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}
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} else if (old && !ctr->clock)
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ctr_tick(ctr, pit);
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}
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}
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void
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pit_ctr_set_clock(ctr_t *ctr, int clock, void *priv)
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{
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pit_ctr_set_clock_common(ctr, clock, priv);
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}
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void
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pit_ctr_set_using_timer(void *data, int counter_id, int using_timer)
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{
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if (tsc > 0)
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timer_process();
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pit_t *pit = (pit_t *) data;
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ctr_t *ctr = &pit->counters[counter_id];
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ctr->using_timer = using_timer;
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}
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static void
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pit_timer_over(void *priv)
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{
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pit_t *dev = (pit_t *) priv;
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dev->clock ^= 1;
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for (uint8_t i = 0; i < NUM_COUNTERS; i++)
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pit_ctr_set_clock_common(&dev->counters[i], dev->clock, dev);
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|
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timer_advance_u64(&dev->callback_timer, dev->pit_const >> 1ULL);
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}
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|
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static void
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pit_write(uint16_t addr, uint8_t val, void *priv)
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{
|
|
pit_t *dev = (pit_t *) priv;
|
|
int t = (addr & 3);
|
|
ctr_t *ctr;
|
|
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("[%04X:%08X] pit_write(%04X, %02X, %016" PRIX64 ")\n",
|
|
CS, cpu_state.pc, addr, val, (uint64_t) (uintptr_t) priv);
|
|
}
|
|
|
|
switch (addr & 3) {
|
|
case 3: /* control */
|
|
t = val >> 6;
|
|
|
|
if (t == 3) {
|
|
if (dev->flags & PIT_8254) {
|
|
/* This is 8254-only. */
|
|
if (!(val & 0x20)) {
|
|
if (val & 2)
|
|
ctr_latch_count(&dev->counters[0]);
|
|
if (val & 4)
|
|
ctr_latch_count(&dev->counters[1]);
|
|
if (val & 8)
|
|
ctr_latch_count(&dev->counters[2]);
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i: Initiated readback command\n", t);
|
|
}
|
|
}
|
|
if (!(val & 0x10)) {
|
|
if (val & 2)
|
|
ctr_latch_status(&dev->counters[0]);
|
|
if (val & 4)
|
|
ctr_latch_status(&dev->counters[1]);
|
|
if (val & 8)
|
|
ctr_latch_status(&dev->counters[2]);
|
|
}
|
|
}
|
|
} else {
|
|
dev->ctrl = val;
|
|
ctr = &dev->counters[t];
|
|
|
|
if (!(dev->ctrl & 0x30)) {
|
|
ctr_latch_count(ctr);
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i: Initiated latched read, %i bytes latched\n",
|
|
t, ctr->latched);
|
|
}
|
|
} else {
|
|
ctr->ctrl = val;
|
|
ctr->rm = ctr->wm = (ctr->ctrl >> 4) & 3;
|
|
ctr->m = (val >> 1) & 7;
|
|
if (ctr->m > 5)
|
|
ctr->m &= 3;
|
|
ctr->null_count = 1;
|
|
ctr->bcd = (ctr->ctrl & 0x01);
|
|
ctr_set_out(ctr, !!ctr->m, dev);
|
|
ctr->state = 0;
|
|
if (ctr->latched) {
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i: Reload while counter is latched\n", t);
|
|
}
|
|
ctr->rl--;
|
|
}
|
|
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i: M = %i, RM/WM = %i, State = %i, Out = %i\n", t, ctr->m, ctr->rm, ctr->state, ctr->out);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0:
|
|
case 1:
|
|
case 2: /* the actual timers */
|
|
ctr = &dev->counters[t];
|
|
|
|
switch (ctr->wm) {
|
|
case 0:
|
|
/* This should never happen. */
|
|
break;
|
|
case 1:
|
|
ctr->l = val;
|
|
ctr->lback = ctr->l;
|
|
ctr->lback2 = ctr->l;
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i (1): Written byte %02X, latch now %04X\n", t, val, ctr->l);
|
|
}
|
|
if (ctr->m == 0)
|
|
ctr_set_out(ctr, 0, dev);
|
|
ctr_load(ctr);
|
|
break;
|
|
case 2:
|
|
ctr->l = (val << 8);
|
|
ctr->lback = ctr->l;
|
|
ctr->lback2 = ctr->l;
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i (2): Written byte %02X, latch now %04X\n", t, val, ctr->l);
|
|
}
|
|
if (ctr->m == 0)
|
|
ctr_set_out(ctr, 0, dev);
|
|
ctr_load(ctr);
|
|
break;
|
|
case 3:
|
|
case 0x83:
|
|
if (ctr->wm & 0x80) {
|
|
ctr->l = (ctr->l & 0x00ff) | (val << 8);
|
|
ctr->lback = ctr->l;
|
|
ctr->lback2 = ctr->l;
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i (0x83): Written high byte %02X, latch now %04X\n", t, val, ctr->l);
|
|
}
|
|
ctr_load(ctr);
|
|
} else {
|
|
ctr->l = (ctr->l & 0xff00) | val;
|
|
ctr->lback = ctr->l;
|
|
ctr->lback2 = ctr->l;
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("PIT %i (3): Written low byte %02X, latch now %04X\n", t, val, ctr->l);
|
|
}
|
|
if (ctr->m == 0) {
|
|
ctr->state = 0;
|
|
ctr_set_out(ctr, 0, dev);
|
|
}
|
|
}
|
|
if (ctr->wm & 0x80)
|
|
ctr->wm &= ~0x80;
|
|
else
|
|
ctr->wm |= 0x80;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
extern uint8_t *ram;
|
|
|
|
uint8_t
|
|
pit_read_reg(void *priv, uint8_t reg)
|
|
{
|
|
pit_t *dev = (pit_t *) priv;
|
|
uint8_t ret = 0xff;
|
|
|
|
switch (reg) {
|
|
case 0x00:
|
|
case 0x02:
|
|
case 0x04:
|
|
ret = dev->counters[reg >> 1].l & 0xff;
|
|
break;
|
|
case 0x01:
|
|
case 0x03:
|
|
case 0x05:
|
|
ret = (dev->counters[reg >> 1].l >> 8) & 0xff;
|
|
break;
|
|
case 0x06:
|
|
ret = dev->ctrl;
|
|
break;
|
|
case 0x07:
|
|
/* The SiS 551x datasheet is unclear about how exactly
|
|
this register is structured.
|
|
Update: But the SiS 5571 datasheet is clear. */
|
|
ret = (dev->counters[0].rm & 0x80) ? 0x01 : 0x00;
|
|
ret |= (dev->counters[1].rm & 0x80) ? 0x02 : 0x00;
|
|
ret |= (dev->counters[2].rm & 0x80) ? 0x04 : 0x00;
|
|
ret |= (dev->counters[0].wm & 0x80) ? 0x08 : 0x00;
|
|
ret |= (dev->counters[1].wm & 0x80) ? 0x10 : 0x00;
|
|
ret |= (dev->counters[2].wm & 0x80) ? 0x20 : 0x00;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint8_t
|
|
pit_read(uint16_t addr, void *priv)
|
|
{
|
|
pit_t *dev = (pit_t *) priv;
|
|
uint8_t ret = 0xff;
|
|
int count;
|
|
int t = (addr & 3);
|
|
ctr_t *ctr;
|
|
|
|
switch (addr & 3) {
|
|
case 3: /* Control. */
|
|
/* This is 8254-only, 8253 returns 0x00. */
|
|
ret = (dev->flags & PIT_8254) ? dev->ctrl : 0x00;
|
|
break;
|
|
|
|
case 0:
|
|
case 1:
|
|
case 2: /* The actual timers. */
|
|
ctr = &dev->counters[t];
|
|
|
|
if (ctr->do_read_status) {
|
|
ctr->do_read_status = 0;
|
|
ret = ctr->read_status;
|
|
break;
|
|
}
|
|
|
|
count = (ctr->state == 1) ? ctr->l : ctr->count;
|
|
|
|
if (ctr->latched) {
|
|
ret = (ctr->rl) >> ((ctr->rm & 0x80) ? 8 : 0);
|
|
|
|
if (ctr->rm & 0x80)
|
|
ctr->rm &= ~0x80;
|
|
else
|
|
ctr->rm |= 0x80;
|
|
|
|
ctr->latched--;
|
|
} else
|
|
switch (ctr->rm) {
|
|
case 0:
|
|
case 0x80:
|
|
ret = 0x00;
|
|
break;
|
|
|
|
case 1:
|
|
ret = count & 0xff;
|
|
break;
|
|
|
|
case 2:
|
|
ret = count >> 8;
|
|
break;
|
|
|
|
case 3:
|
|
case 0x83:
|
|
/* Yes, wm is correct here - this is to ensure correct readout while the
|
|
count is being written. */
|
|
if (ctr->wm & 0x80)
|
|
ret = ~(ctr->l & 0xff);
|
|
else
|
|
ret = count >> ((ctr->rm & 0x80) ? 8 : 0);
|
|
|
|
if (ctr->rm & 0x80)
|
|
ctr->rm &= ~0x80;
|
|
else
|
|
ctr->rm |= 0x80;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if ((dev->flags & (PIT_8254 | PIT_EXT_IO))) {
|
|
pit_log("[%04X:%08X] pit_read(%04X, %016" PRIX64 ") = %02X\n",
|
|
CS, cpu_state.pc, addr, (uint64_t) (uintptr_t) priv, ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
pit_irq0_timer_ps2(int new_out, int old_out, UNUSED(void *priv))
|
|
{
|
|
if (new_out && !old_out) {
|
|
picint(1);
|
|
pit_devs[1].set_gate(pit_devs[1].data, 0, 1);
|
|
}
|
|
|
|
if (!new_out)
|
|
picintc(1);
|
|
|
|
if (!new_out && old_out)
|
|
pit_devs[1].ctr_clock(pit_devs[1].data, 0);
|
|
}
|
|
|
|
void
|
|
pit_refresh_timer_xt(int new_out, int old_out, UNUSED(void *priv))
|
|
{
|
|
if (new_out && !old_out)
|
|
dma_channel_read(0);
|
|
}
|
|
|
|
void
|
|
pit_refresh_timer_at(int new_out, int old_out, UNUSED(void *priv))
|
|
{
|
|
if (refresh_at_enable && new_out && !old_out)
|
|
ppi.pb ^= 0x10;
|
|
}
|
|
|
|
void
|
|
pit_speaker_timer(int new_out, UNUSED(int old_out), UNUSED(void *priv))
|
|
{
|
|
int l;
|
|
|
|
if (cassette != NULL)
|
|
pc_cas_set_out(cassette, new_out);
|
|
|
|
speaker_update();
|
|
|
|
uint16_t count = pit_devs[0].get_count(pit_devs[0].data, 2);
|
|
l = count ? count : 0x10000;
|
|
if (l < 25)
|
|
speakon = 0;
|
|
else
|
|
speakon = new_out;
|
|
|
|
ppispeakon = new_out;
|
|
}
|
|
|
|
void
|
|
pit_nmi_timer_ps2(int new_out, UNUSED(int old_out), UNUSED(void *priv))
|
|
{
|
|
nmi = new_out;
|
|
|
|
if (nmi)
|
|
nmi_auto_clear = 1;
|
|
}
|
|
|
|
static void
|
|
ctr_reset(ctr_t *ctr)
|
|
{
|
|
ctr->ctrl = 0;
|
|
ctr->m = 0;
|
|
ctr->gate = 0;
|
|
ctr->l = 0xffff;
|
|
ctr->using_timer = 1;
|
|
ctr->state = 0;
|
|
ctr->null_count = 1;
|
|
|
|
ctr->latch = 0;
|
|
|
|
ctr->s1_det = 0;
|
|
ctr->l_det = 0;
|
|
}
|
|
|
|
void
|
|
pit_device_reset(pit_t *dev)
|
|
{
|
|
dev->clock = 0;
|
|
|
|
for (uint8_t i = 0; i < NUM_COUNTERS; i++)
|
|
ctr_reset(&dev->counters[i]);
|
|
}
|
|
|
|
void
|
|
pit_reset(pit_t *dev)
|
|
{
|
|
memset(dev, 0, sizeof(pit_t));
|
|
|
|
dev->clock = 0;
|
|
|
|
for (uint8_t i = 0; i < NUM_COUNTERS; i++)
|
|
ctr_reset(&dev->counters[i]);
|
|
|
|
/* Disable speaker gate. */
|
|
dev->counters[2].gate = 0;
|
|
}
|
|
|
|
void
|
|
pit_handler(int set, uint16_t base, int size, void *priv)
|
|
{
|
|
io_handler(set, base, size, pit_read, NULL, NULL, pit_write, NULL, NULL, priv);
|
|
}
|
|
|
|
void
|
|
pit_set_pit_const(void *data, uint64_t pit_const)
|
|
{
|
|
pit_t *pit = (pit_t *) data;
|
|
|
|
pit->pit_const = pit_const;
|
|
}
|
|
|
|
static void
|
|
pit_speed_changed(void *priv)
|
|
{
|
|
pit_set_pit_const(priv, PITCONST);
|
|
}
|
|
|
|
static void
|
|
pit_close(void *priv)
|
|
{
|
|
pit_t *dev = (pit_t *) priv;
|
|
|
|
if (dev == pit_devs[0].data)
|
|
pit_devs[0].data = NULL;
|
|
|
|
if (dev == pit_devs[1].data)
|
|
pit_devs[1].data = NULL;
|
|
|
|
if (dev != NULL)
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
pit_init(const device_t *info)
|
|
{
|
|
pit_t *dev = (pit_t *) malloc(sizeof(pit_t));
|
|
|
|
pit_reset(dev);
|
|
|
|
pit_set_pit_const(dev, PITCONST);
|
|
|
|
if (!(dev->flags & PIT_PS2) && !(dev->flags & PIT_CUSTOM_CLOCK)) {
|
|
timer_add(&dev->callback_timer, pit_timer_over, (void *) dev, 0);
|
|
timer_set_delay_u64(&dev->callback_timer, dev->pit_const >> 1ULL);
|
|
}
|
|
|
|
dev->flags = info->local;
|
|
dev->dev_priv = NULL;
|
|
|
|
if (!(dev->flags & PIT_EXT_IO)) {
|
|
io_sethandler((dev->flags & PIT_SECONDARY) ? 0x0048 : 0x0040, 0x0004,
|
|
pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
|
|
}
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t i8253_device = {
|
|
.name = "Intel 8253/8253-5 Programmable Interval Timer",
|
|
.internal_name = "i8253",
|
|
.flags = DEVICE_ISA | DEVICE_PIT,
|
|
.local = PIT_8253,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = pit_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i8253_ext_io_device = {
|
|
.name = "Intel 8253 Programmable Interval Timer (External I/O)",
|
|
.internal_name = "i8253_ext_io",
|
|
.flags = DEVICE_ISA,
|
|
.local = PIT_8253 | PIT_EXT_IO,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i8254_device = {
|
|
.name = "Intel 8254 Programmable Interval Timer",
|
|
.internal_name = "i8254",
|
|
.flags = DEVICE_ISA | DEVICE_PIT,
|
|
.local = PIT_8254,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = pit_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i8254_sec_device = {
|
|
.name = "Intel 8254 Programmable Interval Timer (Secondary)",
|
|
.internal_name = "i8254_sec",
|
|
.flags = DEVICE_ISA,
|
|
.local = PIT_8254 | PIT_SECONDARY,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = pit_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i8254_ext_io_device = {
|
|
.name = "Intel 8254 Programmable Interval Timer (External I/O)",
|
|
.internal_name = "i8254_ext_io",
|
|
.flags = DEVICE_ISA,
|
|
.local = PIT_8254 | PIT_EXT_IO,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i8254_ps2_device = {
|
|
.name = "Intel 8254 Programmable Interval Timer (PS/2)",
|
|
.internal_name = "i8254_ps2",
|
|
.flags = DEVICE_ISA,
|
|
.local = PIT_8254 | PIT_PS2 | PIT_EXT_IO,
|
|
.init = pit_init,
|
|
.close = pit_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = pit_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
pit_t *
|
|
pit_common_init(int type, void (*out0)(int new_out, int old_out, void *priv), void (*out1)(int new_out, int old_out, void *priv))
|
|
{
|
|
void *pit;
|
|
|
|
pit_intf_t *pit_intf = &pit_devs[0];
|
|
|
|
switch (type) {
|
|
default:
|
|
case PIT_8253:
|
|
pit = device_add(&i8253_device);
|
|
*pit_intf = pit_classic_intf;
|
|
break;
|
|
case PIT_8254:
|
|
pit = device_add(&i8254_device);
|
|
*pit_intf = pit_classic_intf;
|
|
break;
|
|
case PIT_8253_FAST:
|
|
pit = device_add(&i8253_fast_device);
|
|
*pit_intf = pit_fast_intf;
|
|
break;
|
|
case PIT_8254_FAST:
|
|
pit = device_add(&i8254_fast_device);
|
|
*pit_intf = pit_fast_intf;
|
|
break;
|
|
}
|
|
|
|
pit_intf->data = pit;
|
|
|
|
for (uint8_t i = 0; i < 3; i++) {
|
|
pit_intf->set_gate(pit_intf->data, i, 1);
|
|
pit_intf->set_using_timer(pit_intf->data, i, 1);
|
|
}
|
|
|
|
pit_intf->set_out_func(pit_intf->data, 0, out0);
|
|
pit_intf->set_out_func(pit_intf->data, 1, out1);
|
|
pit_intf->set_out_func(pit_intf->data, 2, pit_speaker_timer);
|
|
pit_intf->set_load_func(pit_intf->data, 2, speaker_set_count);
|
|
|
|
pit_intf->set_gate(pit_intf->data, 2, 0);
|
|
|
|
return pit;
|
|
}
|
|
|
|
pit_t *
|
|
pit_ps2_init(int type)
|
|
{
|
|
void *pit;
|
|
|
|
pit_intf_t *ps2_pit = &pit_devs[1];
|
|
|
|
switch (type) {
|
|
default:
|
|
case PIT_8254:
|
|
pit = device_add(&i8254_ps2_device);
|
|
*ps2_pit = pit_classic_intf;
|
|
break;
|
|
|
|
case PIT_8254_FAST:
|
|
pit = device_add(&i8254_ps2_fast_device);
|
|
*ps2_pit = pit_fast_intf;
|
|
break;
|
|
}
|
|
|
|
ps2_pit->data = pit;
|
|
|
|
ps2_pit->set_gate(ps2_pit->data, 0, 0);
|
|
for (int i = 0; i < 3; i++) {
|
|
ps2_pit->set_using_timer(ps2_pit->data, i, 0);
|
|
}
|
|
|
|
io_sethandler(0x0044, 0x0001, ps2_pit->read, NULL, NULL, ps2_pit->write, NULL, NULL, pit);
|
|
io_sethandler(0x0047, 0x0001, ps2_pit->read, NULL, NULL, ps2_pit->write, NULL, NULL, pit);
|
|
|
|
pit_devs[0].set_out_func(pit_devs[0].data, 0, pit_irq0_timer_ps2);
|
|
ps2_pit->set_out_func(ps2_pit->data, 0, pit_nmi_timer_ps2);
|
|
|
|
return pit;
|
|
}
|
|
|
|
void
|
|
pit_change_pas16_consts(double prescale)
|
|
{
|
|
PAS16CONST = (uint64_t) ((PAS16CONSTD / prescale) * (double) (1ULL << 32));
|
|
PAS16CONST2 = (uint64_t) ((PAS16CONST2D / prescale) * (double) (1ULL << 32));
|
|
}
|
|
|
|
void
|
|
pit_set_clock(uint32_t clock)
|
|
{
|
|
/* Set default CPU/crystal clock and xt_cpu_multi. */
|
|
if (cpu_s->cpu_type >= CPU_286) {
|
|
uint32_t remainder = (clock % 100000000);
|
|
if (remainder == 66666666)
|
|
cpuclock = (double) (clock - remainder) + (200000000.0 / 3.0);
|
|
else if (remainder == 33333333)
|
|
cpuclock = (double) (clock - remainder) + (100000000.0 / 3.0);
|
|
else
|
|
cpuclock = (double) clock;
|
|
|
|
PITCONSTD = (cpuclock / 1193182.0);
|
|
PITCONST = (uint64_t) (PITCONSTD * (double) (1ULL << 32));
|
|
#ifdef IMPRECISE_CGACONST
|
|
CGACONST = (uint64_t) ((cpuclock / (19687503.0 / 11.0)) * (double) (1ULL << 32));
|
|
#else
|
|
CGACONST = (uint64_t) ((cpuclock / (157500000.0 / 88.0)) * (double) (1ULL << 32));
|
|
#endif
|
|
ISACONST = (uint64_t) ((cpuclock / (double) cpu_isa_speed) * (double) (1ULL << 32));
|
|
xt_cpu_multi = 1ULL;
|
|
} else {
|
|
cpuclock = (157500000.0 / 11.0);
|
|
PITCONSTD = 12.0;
|
|
PITCONST = (12ULL << 32ULL);
|
|
CGACONST = (8ULL << 32ULL);
|
|
xt_cpu_multi = 3ULL;
|
|
|
|
switch (cpu_s->rspeed) {
|
|
case 7159092:
|
|
if (cpu_s->cpu_flags & CPU_ALTERNATE_XTAL) {
|
|
cpuclock = 28636368.0;
|
|
xt_cpu_multi = 4ULL;
|
|
} else
|
|
xt_cpu_multi = 2ULL;
|
|
break;
|
|
|
|
case 8000000:
|
|
cpuclock = 24000000.0;
|
|
break;
|
|
case 9545456:
|
|
cpuclock = 28636368.0;
|
|
break;
|
|
case 10000000:
|
|
cpuclock = 30000000.0;
|
|
break;
|
|
case 12000000:
|
|
cpuclock = 36000000.0;
|
|
break;
|
|
case 16000000:
|
|
cpuclock = 48000000.0;
|
|
break;
|
|
|
|
default:
|
|
if (cpu_s->cpu_flags & CPU_ALTERNATE_XTAL) {
|
|
cpuclock = 28636368.0;
|
|
xt_cpu_multi = 6ULL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (cpuclock == 28636368.0) {
|
|
PITCONSTD = 24.0;
|
|
PITCONST = (24ULL << 32LL);
|
|
CGACONST = (16ULL << 32LL);
|
|
} else if (cpuclock != 14318184.0) {
|
|
PITCONSTD = (cpuclock / 1193182.0);
|
|
PITCONST = (uint64_t) (PITCONSTD * (double) (1ULL << 32));
|
|
#ifdef IMPRECISE_CGACONST
|
|
CGACONST = (uint64_t) ((cpuclock / (19687503.0 / 11.0)) * (double) (1ULL << 32));
|
|
#else
|
|
CGACONST = (uint64_t) ((cpuclock / (157500000.0 / 88.0)) * (double) (1ULL << 32));
|
|
#endif
|
|
}
|
|
|
|
ISACONST = (1ULL << 32ULL);
|
|
}
|
|
xt_cpu_multi <<= 32ULL;
|
|
|
|
/* Delay for empty I/O ports. */
|
|
io_delay = (int) round(((double) cpu_s->rspeed) / 3000000.0);
|
|
|
|
#ifdef WRONG_MDACONST
|
|
MDACONST = (uint64_t) (cpuclock / 2032125.0 * (double) (1ULL << 32));
|
|
#else
|
|
MDACONST = (uint64_t) (cpuclock / (16257000.0 / 9.0) * (double) (1ULL << 32));
|
|
#endif
|
|
HERCCONST = MDACONST;
|
|
VGACONST1 = (uint64_t) (cpuclock / 25175000.0 * (double) (1ULL << 32));
|
|
VGACONST2 = (uint64_t) (cpuclock / 28322000.0 * (double) (1ULL << 32));
|
|
RTCCONST = (uint64_t) (cpuclock / 32768.0 * (double) (1ULL << 32));
|
|
|
|
TIMER_USEC = (uint64_t) ((cpuclock / 1000000.0) * (double) (1ULL << 32));
|
|
|
|
PAS16CONSTD = (cpuclock / 441000.0);
|
|
PAS16CONST = (uint64_t) (PAS16CONSTD * (double) (1ULL << 32));
|
|
|
|
PAS16CONST2D = (cpuclock / 1008000.0);
|
|
PAS16CONST2 = (uint64_t) (PAS16CONST2D * (double) (1ULL << 32));
|
|
|
|
PASSCSICONSTD = (cpuclock / (28224000.0 / 14.0));
|
|
PASSCSICONST = (uint64_t) (PASSCSICONSTD * (double) (1ULL << 32));
|
|
|
|
isa_timing = (cpuclock / (double) cpu_isa_speed);
|
|
if (cpu_64bitbus)
|
|
bus_timing = (cpuclock / (cpu_busspeed / 2));
|
|
else
|
|
bus_timing = (cpuclock / cpu_busspeed);
|
|
pci_timing = (cpuclock / (double) cpu_pci_speed);
|
|
agp_timing = (cpuclock / (double) cpu_agp_speed);
|
|
|
|
/* PCICLK in us for use with timer_on_auto(). */
|
|
PCICLK = pci_timing / (cpuclock / 1000000.0);
|
|
AGPCLK = agp_timing / (cpuclock / 1000000.0);
|
|
|
|
if (cpu_busspeed >= 30000000)
|
|
SYSCLK = bus_timing * 4.0;
|
|
else
|
|
SYSCLK = bus_timing * 3.0;
|
|
|
|
video_update_timing();
|
|
|
|
device_speed_changed();
|
|
}
|
|
|
|
const pit_intf_t pit_classic_intf = {
|
|
.read = &pit_read,
|
|
.write = &pit_write,
|
|
.get_count = &pit_ctr_get_count,
|
|
.set_gate = &pit_ctr_set_gate,
|
|
.set_using_timer = &pit_ctr_set_using_timer,
|
|
.set_out_func = &pit_ctr_set_out_func,
|
|
.set_load_func = &pit_ctr_set_load_func,
|
|
.ctr_clock = &ctr_clock,
|
|
.set_pit_const = &pit_set_pit_const,
|
|
.data = NULL,
|
|
};
|