1030 lines
21 KiB
C
1030 lines
21 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel DMA controllers.
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*
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*
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*
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* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
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* Miran Grca, <mgrca8@gmail.com>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2008-2020 Sarah Walker.
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* Copyright 2016-2020 Miran Grca.
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* Copyright 2017-2020 Fred N. van Kempen.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu_common/cpu.h"
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#include "cpu_common/x86.h"
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#include <86box/machine.h>
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#include <86box/mca.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/dma.h>
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dma_t dma[8];
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uint8_t dma_e;
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static uint8_t dmaregs[16];
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static uint8_t dma16regs[16];
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static uint8_t dmapages[16];
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static int dma_wp,
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dma16_wp;
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static uint8_t dma_m;
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static uint8_t dma_stat;
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static uint8_t dma_stat_rq;
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static uint8_t dma_stat_rq_pc;
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static uint8_t dma_command,
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dma16_command;
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static uint8_t dma_req_is_soft;
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static uint8_t dma_buffer[65536];
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static uint16_t dma16_buffer[65536];
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static struct {
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int xfr_command,
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xfr_channel;
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int byte_ptr;
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int is_ps2;
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} dma_ps2;
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#define DMA_PS2_IOA (1 << 0)
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#define DMA_PS2_XFER_MEM_TO_IO (1 << 2)
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#define DMA_PS2_XFER_IO_TO_MEM (3 << 2)
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#define DMA_PS2_XFER_MASK (3 << 2)
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#define DMA_PS2_DEC2 (1 << 4)
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#define DMA_PS2_SIZE16 (1 << 6)
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static void dma_ps2_run(int channel);
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int
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dma_get_drq(int channel)
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{
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return !!(dma_stat_rq_pc & (1 << channel));
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}
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void
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dma_set_drq(int channel, int set)
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{
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dma_stat_rq_pc &= ~(1 << channel);
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if (set)
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dma_stat_rq_pc |= (1 << channel);
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}
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static void
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dma_block_transfer(int channel)
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{
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int i, bit16;
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bit16 = (channel >= 4);
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dma_req_is_soft = 1;
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for (i = 0; i <= dma[channel].cb; i++) {
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if ((dma[channel].mode & 0x8c) == 0x84) {
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if (bit16)
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dma_channel_write(channel, dma16_buffer[i]);
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else
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dma_channel_write(channel, dma_buffer[i]);
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} else if ((dma[channel].mode & 0x8c) == 0x88) {
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if (bit16)
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dma16_buffer[i] = dma_channel_read(channel);
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else
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dma_buffer[i] = dma_channel_read(channel);
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}
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}
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dma_req_is_soft = 0;
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}
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static uint8_t
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dma_read(uint16_t addr, void *priv)
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{
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int channel = (addr >> 1) & 3;
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uint8_t temp;
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switch (addr & 0xf) {
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case 0:
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case 2:
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case 4:
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case 6: /*Address registers*/
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dma_wp ^= 1;
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if (dma_wp)
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return(dma[channel].ac & 0xff);
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return((dma[channel].ac >> 8) & 0xff);
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case 1:
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case 3:
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case 5:
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case 7: /*Count registers*/
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dma_wp ^= 1;
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if (dma_wp)
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temp = dma[channel].cc & 0xff;
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else
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temp = dma[channel].cc >> 8;
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return(temp);
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case 8: /*Status register*/
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temp = dma_stat_rq_pc & 0xf;
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temp <<= 4;
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temp |= dma_stat & 0xf;
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dma_stat &= ~0xf;
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return(temp);
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case 0xd: /*Temporary register*/
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return(0);
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}
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return(dmaregs[addr & 0xf]);
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}
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static void
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dma_write(uint16_t addr, uint8_t val, void *priv)
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{
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int channel = (addr >> 1) & 3;
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dmaregs[addr & 0xf] = val;
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switch (addr & 0xf) {
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case 0:
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case 2:
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case 4:
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case 6: /*Address registers*/
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dma_wp ^= 1;
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if (dma_wp)
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dma[channel].ab = (dma[channel].ab & 0xffff00) | val;
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else
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dma[channel].ab = (dma[channel].ab & 0xff00ff) | (val << 8);
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dma[channel].ac = dma[channel].ab;
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return;
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case 1:
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case 3:
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case 5:
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case 7: /*Count registers*/
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dma_wp ^= 1;
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if (dma_wp)
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dma[channel].cb = (dma[channel].cb & 0xff00) | val;
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else
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dma[channel].cb = (dma[channel].cb & 0x00ff) | (val << 8);
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dma[channel].cc = dma[channel].cb;
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return;
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case 8: /*Control register*/
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dma_command = val;
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if (val & 0x01)
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fatal("Memory-to-memory enable\n");
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return;
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case 9: /*Request register */
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channel = (val & 3);
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if (val & 4) {
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dma_stat_rq_pc |= (1 << channel);
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dma_block_transfer(channel);
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} else
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dma_stat_rq_pc &= ~(1 << channel);
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break;
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case 0xa: /*Mask*/
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channel = (val & 3);
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if (val & 4)
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dma_m |= (1 << channel);
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else
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dma_m &= ~(1 << channel);
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return;
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case 0xb: /*Mode*/
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channel = (val & 3);
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dma[channel].mode = val;
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if (dma_ps2.is_ps2) {
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dma[channel].ps2_mode &= ~0x1c;
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if (val & 0x20)
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dma[channel].ps2_mode |= 0x10;
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if ((val & 0xc) == 8)
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dma[channel].ps2_mode |= 4;
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else if ((val & 0xc) == 4)
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dma[channel].ps2_mode |= 0xc;
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}
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return;
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case 0xc: /*Clear FF*/
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dma_wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma_wp = 0;
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dma_m |= 0xf;
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dma_stat_rq_pc &= ~0x0f;
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return;
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case 0xe: /*Clear mask*/
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dma_m &= 0xf0;
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return;
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case 0xf: /*Mask write*/
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dma_m = (dma_m & 0xf0) | (val & 0xf);
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return;
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}
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}
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static uint8_t
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dma_ps2_read(uint16_t addr, void *priv)
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{
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dma_t *dma_c = &dma[dma_ps2.xfr_channel];
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uint8_t temp = 0xff;
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switch (addr) {
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case 0x1a:
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switch (dma_ps2.xfr_command) {
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case 2: /*Address*/
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case 3:
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switch (dma_ps2.byte_ptr) {
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case 0:
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temp = dma_c->ac & 0xff;
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dma_ps2.byte_ptr = 1;
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break;
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case 1:
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temp = (dma_c->ac >> 8) & 0xff;
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dma_ps2.byte_ptr = 2;
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break;
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case 2:
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temp = (dma_c->ac >> 16) & 0xff;
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dma_ps2.byte_ptr = 0;
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break;
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}
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break;
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case 4: /*Count*/
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case 5:
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if (dma_ps2.byte_ptr)
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temp = dma_c->cc >> 8;
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else
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temp = dma_c->cc & 0xff;
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dma_ps2.byte_ptr = (dma_ps2.byte_ptr + 1) & 1;
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break;
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case 6: /*Read DMA status*/
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if (dma_ps2.byte_ptr) {
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temp = ((dma_stat_rq & 0xf0) >> 4) | (dma_stat & 0xf0);
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dma_stat &= ~0xf0;
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dma_stat_rq &= ~0xf0;
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} else {
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temp = (dma_stat_rq & 0xf) | ((dma_stat & 0xf) << 4);
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dma_stat &= ~0xf;
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dma_stat_rq &= ~0xf;
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}
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dma_ps2.byte_ptr = (dma_ps2.byte_ptr + 1) & 1;
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break;
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case 7: /*Mode*/
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temp = dma_c->ps2_mode;
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break;
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case 8: /*Arbitration Level*/
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temp = dma_c->arb_level;
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break;
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default:
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fatal("Bad XFR Read command %i channel %i\n", dma_ps2.xfr_command, dma_ps2.xfr_channel);
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}
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break;
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}
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return(temp);
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}
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static void
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dma_ps2_write(uint16_t addr, uint8_t val, void *priv)
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{
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dma_t *dma_c = &dma[dma_ps2.xfr_channel];
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uint8_t mode;
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switch (addr) {
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case 0x18:
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dma_ps2.xfr_channel = val & 0x7;
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dma_ps2.xfr_command = val >> 4;
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dma_ps2.byte_ptr = 0;
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switch (dma_ps2.xfr_command) {
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case 9: /*Set DMA mask*/
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dma_m |= (1 << dma_ps2.xfr_channel);
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break;
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case 0xa: /*Reset DMA mask*/
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dma_m &= ~(1 << dma_ps2.xfr_channel);
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break;
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case 0xb:
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if (!(dma_m & (1 << dma_ps2.xfr_channel)))
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dma_ps2_run(dma_ps2.xfr_channel);
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break;
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}
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break;
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case 0x1a:
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switch (dma_ps2.xfr_command) {
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case 0: /*I/O address*/
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if (dma_ps2.byte_ptr)
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dma_c->io_addr = (dma_c->io_addr & 0x00ff) | (val << 8);
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else
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dma_c->io_addr = (dma_c->io_addr & 0xff00) | val;
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dma_ps2.byte_ptr = (dma_ps2.byte_ptr + 1) & 1;
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break;
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case 2: /*Address*/
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switch (dma_ps2.byte_ptr) {
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case 0:
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dma_c->ac = (dma_c->ac & 0xffff00) | val;
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dma_ps2.byte_ptr = 1;
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break;
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case 1:
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dma_c->ac = (dma_c->ac & 0xff00ff) | (val << 8);
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dma_ps2.byte_ptr = 2;
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break;
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case 2:
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dma_c->ac = (dma_c->ac & 0x00ffff) | (val << 16);
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dma_ps2.byte_ptr = 0;
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break;
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}
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dma_c->ab = dma_c->ac;
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break;
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case 4: /*Count*/
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if (dma_ps2.byte_ptr)
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dma_c->cc = (dma_c->cc & 0xff) | (val << 8);
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else
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dma_c->cc = (dma_c->cc & 0xff00) | val;
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dma_ps2.byte_ptr = (dma_ps2.byte_ptr + 1) & 1;
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dma_c->cb = dma_c->cc;
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break;
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case 7: /*Mode register*/
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mode = 0;
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if (val & DMA_PS2_DEC2)
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mode |= 0x20;
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if ((val & DMA_PS2_XFER_MASK) == DMA_PS2_XFER_MEM_TO_IO)
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mode |= 8;
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else if ((val & DMA_PS2_XFER_MASK) == DMA_PS2_XFER_IO_TO_MEM)
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mode |= 4;
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dma_c->mode = (dma_c->mode & ~0x2c) | mode;
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dma_c->ps2_mode = val;
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dma_c->size = val & DMA_PS2_SIZE16;
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break;
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case 8: /*Arbitration Level*/
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dma_c->arb_level = val;
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break;
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default:
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fatal("Bad XFR command %i channel %i val %02x\n", dma_ps2.xfr_command, dma_ps2.xfr_channel, val);
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}
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break;
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}
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}
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static uint8_t
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dma16_read(uint16_t addr, void *priv)
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{
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int channel = ((addr >> 2) & 3) + 4;
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uint8_t temp;
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addr >>= 1;
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switch (addr & 0xf) {
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case 0:
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case 2:
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case 4:
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case 6: /*Address registers*/
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dma16_wp ^= 1;
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if (dma_ps2.is_ps2) {
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if (dma16_wp)
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return(dma[channel].ac);
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return((dma[channel].ac >> 8) & 0xff);
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}
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if (dma16_wp)
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return((dma[channel].ac >> 1) & 0xff);
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return((dma[channel].ac >> 9) & 0xff);
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case 1:
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case 3:
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case 5:
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case 7: /*Count registers*/
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dma16_wp ^= 1;
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if (dma16_wp)
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temp = dma[channel].cc & 0xff;
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else
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temp = dma[channel].cc >> 8;
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return(temp);
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case 8: /*Status register*/
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temp = (dma_stat_rq_pc & 0xf0);
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temp |= dma_stat >> 4;
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dma_stat &= ~0xf0;
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return(temp);
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}
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return(dma16regs[addr & 0xf]);
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}
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static void
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dma16_write(uint16_t addr, uint8_t val, void *priv)
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{
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int channel = ((addr >> 2) & 3) + 4;
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addr >>= 1;
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dma16regs[addr & 0xf] = val;
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switch (addr & 0xf) {
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case 0:
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case 2:
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case 4:
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case 6: /*Address registers*/
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dma16_wp ^= 1;
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if (dma_ps2.is_ps2) {
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if (dma16_wp)
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dma[channel].ab = (dma[channel].ab & 0xffff00) | val;
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else
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dma[channel].ab = (dma[channel].ab & 0xff00ff) | (val << 8);
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} else {
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if (dma16_wp)
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dma[channel].ab = (dma[channel].ab & 0xfffe00) | (val << 1);
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else
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dma[channel].ab = (dma[channel].ab & 0xfe01ff) | (val << 9);
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}
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dma[channel].ac = dma[channel].ab;
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return;
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case 1:
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case 3:
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case 5:
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case 7: /*Count registers*/
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dma16_wp ^= 1;
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if (dma16_wp)
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dma[channel].cb = (dma[channel].cb & 0xff00) | val;
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else
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dma[channel].cb = (dma[channel].cb & 0x00ff) | (val << 8);
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dma[channel].cc = dma[channel].cb;
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return;
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case 8: /*Control register*/
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return;
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case 9: /*Request register */
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channel = (val & 3) + 4;
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if (val & 4) {
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dma_stat_rq_pc |= (1 << channel);
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dma_block_transfer(channel);
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} else
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dma_stat_rq_pc &= ~(1 << channel);
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break;
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case 0xa: /*Mask*/
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channel = (val & 3);
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if (val & 4)
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dma_m |= (0x10 << channel);
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else
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dma_m &= ~(0x10 << channel);
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return;
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case 0xb: /*Mode*/
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channel = (val & 3) + 4;
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dma[channel].mode = val;
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if (dma_ps2.is_ps2) {
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dma[channel].ps2_mode &= ~0x1c;
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if (val & 0x20)
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dma[channel].ps2_mode |= 0x10;
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if ((val & 0xc) == 8)
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dma[channel].ps2_mode |= 4;
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else if ((val & 0xc) == 4)
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dma[channel].ps2_mode |= 0xc;
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}
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return;
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|
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case 0xc: /*Clear FF*/
|
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dma16_wp = 0;
|
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return;
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|
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case 0xd: /*Master clear*/
|
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dma16_wp = 0;
|
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dma_m |= 0xf0;
|
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dma_stat_rq_pc &= ~0xf0;
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return;
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case 0xe: /*Clear mask*/
|
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dma_m &= 0x0f;
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return;
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|
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case 0xf: /*Mask write*/
|
|
dma_m = (dma_m & 0x0f) | ((val & 0xf) << 4);
|
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return;
|
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}
|
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}
|
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|
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|
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static void
|
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dma_page_write(uint16_t addr, uint8_t val, void *priv)
|
|
{
|
|
dmapages[addr & 0xf] = val;
|
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|
|
switch (addr & 0xf) {
|
|
case 1:
|
|
dma[2].page = (AT) ? val : val & 0xf;
|
|
dma[2].ab = (dma[2].ab & 0xffff) | (dma[2].page << 16);
|
|
dma[2].ac = (dma[2].ac & 0xffff) | (dma[2].page << 16);
|
|
break;
|
|
|
|
case 2:
|
|
dma[3].page = (AT) ? val : val & 0xf;
|
|
dma[3].ab = (dma[3].ab & 0xffff) | (dma[3].page << 16);
|
|
dma[3].ac = (dma[3].ac & 0xffff) | (dma[3].page << 16);
|
|
break;
|
|
|
|
case 3:
|
|
dma[1].page = (AT) ? val : val & 0xf;
|
|
dma[1].ab = (dma[1].ab & 0xffff) | (dma[1].page << 16);
|
|
dma[1].ac = (dma[1].ac & 0xffff) | (dma[1].page << 16);
|
|
break;
|
|
|
|
case 7:
|
|
dma[0].page = (AT) ? val : val & 0xf;
|
|
dma[0].ab = (dma[0].ab & 0xffff) | (dma[0].page << 16);
|
|
dma[0].ac = (dma[0].ac & 0xffff) | (dma[0].page << 16);
|
|
break;
|
|
|
|
case 0x9:
|
|
dma[6].page = val & 0xfe;
|
|
dma[6].ab = (dma[6].ab & 0x1ffff) | (dma[6].page << 16);
|
|
dma[6].ac = (dma[6].ac & 0x1ffff) | (dma[6].page << 16);
|
|
break;
|
|
|
|
case 0xa:
|
|
dma[7].page = val & 0xfe;
|
|
dma[7].ab = (dma[7].ab & 0x1ffff) | (dma[7].page << 16);
|
|
dma[7].ac = (dma[7].ac & 0x1ffff) | (dma[7].page << 16);
|
|
break;
|
|
|
|
case 0xb:
|
|
dma[5].page = val & 0xfe;
|
|
dma[5].ab = (dma[5].ab & 0x1ffff) | (dma[5].page << 16);
|
|
dma[5].ac = (dma[5].ac & 0x1ffff) | (dma[5].page << 16);
|
|
break;
|
|
|
|
case 0xf:
|
|
dma[4].page = val & 0xfe;
|
|
dma[4].ab = (dma[4].ab & 0x1ffff) | (dma[4].page << 16);
|
|
dma[4].ac = (dma[4].ac & 0x1ffff) | (dma[4].page << 16);
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
static uint8_t
|
|
dma_page_read(uint16_t addr, void *priv)
|
|
{
|
|
return(dmapages[addr & 0xf]);
|
|
}
|
|
|
|
|
|
void
|
|
dma_reset(void)
|
|
{
|
|
int c;
|
|
|
|
dma_wp = dma16_wp = 0;
|
|
dma_m = 0;
|
|
|
|
dma_e = 0xff;
|
|
|
|
for (c = 0; c < 16; c++)
|
|
dmaregs[c] = dma16regs[c] = 0;
|
|
for (c = 0; c < 8; c++) {
|
|
dma[c].mode = 0;
|
|
dma[c].ac = 0;
|
|
dma[c].cc = 0;
|
|
dma[c].ab = 0;
|
|
dma[c].cb = 0;
|
|
dma[c].size = (c & 4) ? 1 : 0;
|
|
}
|
|
|
|
dma_stat = 0x00;
|
|
dma_stat_rq = 0x00;
|
|
dma_stat_rq_pc = 0x00;
|
|
dma_req_is_soft = 0;
|
|
|
|
memset(dma_buffer, 0x00, sizeof(dma_buffer));
|
|
memset(dma16_buffer, 0x00, sizeof(dma16_buffer));
|
|
}
|
|
|
|
|
|
void
|
|
dma_init(void)
|
|
{
|
|
dma_reset();
|
|
|
|
io_sethandler(0x0000, 16,
|
|
dma_read,NULL,NULL, dma_write,NULL,NULL, NULL);
|
|
io_sethandler(0x0080, 8,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
dma_ps2.is_ps2 = 0;
|
|
}
|
|
|
|
|
|
void
|
|
dma16_init(void)
|
|
{
|
|
dma_reset();
|
|
|
|
io_sethandler(0x00C0, 32,
|
|
dma16_read,NULL,NULL, dma16_write,NULL,NULL, NULL);
|
|
io_sethandler(0x0088, 8,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
}
|
|
|
|
|
|
void
|
|
dma_alias_set(void)
|
|
{
|
|
io_sethandler(0x0090, 2,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_sethandler(0x0093, 13,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
}
|
|
|
|
|
|
void
|
|
dma_alias_set_piix(void)
|
|
{
|
|
io_sethandler(0x0090, 1,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_sethandler(0x0094, 3,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_sethandler(0x0098, 1,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_sethandler(0x009C, 3,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
}
|
|
|
|
|
|
void
|
|
dma_alias_remove(void)
|
|
{
|
|
io_removehandler(0x0090, 2,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_removehandler(0x0093, 13,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
}
|
|
|
|
|
|
void
|
|
dma_alias_remove_piix(void)
|
|
{
|
|
io_removehandler(0x0090, 1,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_removehandler(0x0094, 3,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_removehandler(0x0098, 1,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
io_removehandler(0x009C, 3,
|
|
dma_page_read,NULL,NULL, dma_page_write,NULL,NULL, NULL);
|
|
}
|
|
|
|
|
|
void
|
|
ps2_dma_init(void)
|
|
{
|
|
dma_reset();
|
|
|
|
io_sethandler(0x0018, 1,
|
|
dma_ps2_read,NULL,NULL, dma_ps2_write,NULL,NULL, NULL);
|
|
io_sethandler(0x001a, 1,
|
|
dma_ps2_read,NULL,NULL, dma_ps2_write,NULL,NULL, NULL);
|
|
dma_ps2.is_ps2 = 1;
|
|
}
|
|
|
|
|
|
uint8_t
|
|
_dma_read(uint32_t addr)
|
|
{
|
|
uint8_t temp = mem_readb_phys(addr);
|
|
|
|
return(temp);
|
|
}
|
|
|
|
|
|
void
|
|
_dma_write(uint32_t addr, uint8_t val)
|
|
{
|
|
mem_writeb_phys(addr, val);
|
|
mem_invalidate_range(addr, addr);
|
|
}
|
|
|
|
|
|
int
|
|
dma_channel_read(int channel)
|
|
{
|
|
dma_t *dma_c = &dma[channel];
|
|
uint16_t temp;
|
|
int tc = 0;
|
|
|
|
if (channel < 4) {
|
|
if (dma_command & 0x04)
|
|
return(DMA_NODATA);
|
|
} else {
|
|
if (dma16_command & 0x04)
|
|
return(DMA_NODATA);
|
|
}
|
|
|
|
if (!(dma_e & (1 << channel)))
|
|
return(DMA_NODATA);
|
|
if ((dma_m & (1 << channel)) && !dma_req_is_soft)
|
|
return(DMA_NODATA);
|
|
if ((dma_c->mode & 0xC) != 8)
|
|
return(DMA_NODATA);
|
|
|
|
if (!AT && !channel)
|
|
refreshread();
|
|
|
|
if (! dma_c->size) {
|
|
temp = _dma_read(dma_c->ac);
|
|
|
|
if (dma_c->mode & 0x20) {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac--;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xff0000) | ((dma_c->ac - 1) & 0xffff);
|
|
} else {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac++;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xff0000) | ((dma_c->ac + 1) & 0xffff);
|
|
}
|
|
} else {
|
|
temp = _dma_read(dma_c->ac) | (_dma_read(dma_c->ac + 1) << 8);
|
|
|
|
if (dma_c->mode & 0x20) {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac -= 2;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xfe0000) | ((dma_c->ac - 2) & 0x1ffff);
|
|
} else {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac += 2;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xfe0000) | ((dma_c->ac + 2) & 0x1ffff);
|
|
}
|
|
}
|
|
|
|
dma_stat_rq |= (1 << channel);
|
|
|
|
dma_c->cc--;
|
|
if (dma_c->cc < 0) {
|
|
tc = 1;
|
|
if (dma_c->mode & 0x10) { /*Auto-init*/
|
|
dma_c->cc = dma_c->cb;
|
|
dma_c->ac = dma_c->ab;
|
|
} else
|
|
dma_m |= (1 << channel);
|
|
dma_stat |= (1 << channel);
|
|
}
|
|
|
|
if (tc)
|
|
return(temp | DMA_OVER);
|
|
|
|
return(temp);
|
|
}
|
|
|
|
|
|
int
|
|
dma_channel_write(int channel, uint16_t val)
|
|
{
|
|
dma_t *dma_c = &dma[channel];
|
|
|
|
if (channel < 4) {
|
|
if (dma_command & 0x04)
|
|
return(DMA_NODATA);
|
|
} else {
|
|
if (dma16_command & 0x04)
|
|
return(DMA_NODATA);
|
|
}
|
|
|
|
if (!(dma_e & (1 << channel)))
|
|
return(DMA_NODATA);
|
|
if ((dma_m & (1 << channel)) && !dma_req_is_soft)
|
|
return(DMA_NODATA);
|
|
if ((dma_c->mode & 0xC) != 4)
|
|
return(DMA_NODATA);
|
|
|
|
if (! dma_c->size) {
|
|
_dma_write(dma_c->ac, val & 0xff);
|
|
|
|
if (dma_c->mode & 0x20) {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac--;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xff0000) | ((dma_c->ac - 1) & 0xffff);
|
|
} else {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac++;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xff0000) | ((dma_c->ac + 1) & 0xffff);
|
|
}
|
|
} else {
|
|
_dma_write(dma_c->ac, val & 0xff);
|
|
_dma_write(dma_c->ac + 1, val >> 8);
|
|
|
|
if (dma_c->mode & 0x20) {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac -= 2;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xfe0000) | ((dma_c->ac - 2) & 0x1ffff);
|
|
dma_c->ac = (dma_c->ac & 0xfe0000) | ((dma_c->ac - 2) & 0x1ffff);
|
|
} else {
|
|
if (dma_ps2.is_ps2)
|
|
dma_c->ac += 2;
|
|
else
|
|
dma_c->ac = (dma_c->ac & 0xfe0000) | ((dma_c->ac + 2) & 0x1ffff);
|
|
}
|
|
}
|
|
|
|
dma_stat_rq |= (1 << channel);
|
|
|
|
dma_c->cc--;
|
|
if (dma_c->cc < 0) {
|
|
if (dma_c->mode & 0x10) { /*Auto-init*/
|
|
dma_c->cc = dma_c->cb;
|
|
dma_c->ac = dma_c->ab;
|
|
} else
|
|
dma_m |= (1 << channel);
|
|
dma_stat |= (1 << channel);
|
|
}
|
|
|
|
if (dma_m & (1 << channel))
|
|
return(DMA_OVER);
|
|
|
|
return(0);
|
|
}
|
|
|
|
|
|
static void
|
|
dma_ps2_run(int channel)
|
|
{
|
|
dma_t *dma_c = &dma[channel];
|
|
|
|
switch (dma_c->ps2_mode & DMA_PS2_XFER_MASK) {
|
|
case DMA_PS2_XFER_MEM_TO_IO:
|
|
do {
|
|
if (! dma_c->size) {
|
|
uint8_t temp = _dma_read(dma_c->ac);
|
|
|
|
outb(dma_c->io_addr, temp);
|
|
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac--;
|
|
else
|
|
dma_c->ac++;
|
|
} else {
|
|
uint16_t temp = _dma_read(dma_c->ac) | (_dma_read(dma_c->ac + 1) << 8);
|
|
|
|
outw(dma_c->io_addr, temp);
|
|
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac -= 2;
|
|
else
|
|
dma_c->ac += 2;
|
|
}
|
|
|
|
dma_stat_rq |= (1 << channel);
|
|
dma_c->cc--;
|
|
} while (dma_c->cc > 0);
|
|
|
|
dma_stat |= (1 << channel);
|
|
break;
|
|
|
|
case DMA_PS2_XFER_IO_TO_MEM:
|
|
do {
|
|
if (! dma_c->size) {
|
|
uint8_t temp = inb(dma_c->io_addr);
|
|
|
|
_dma_write(dma_c->ac, temp);
|
|
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac--;
|
|
else
|
|
dma_c->ac++;
|
|
} else {
|
|
uint16_t temp = inw(dma_c->io_addr);
|
|
|
|
_dma_write(dma_c->ac, temp & 0xff);
|
|
_dma_write(dma_c->ac + 1, temp >> 8);
|
|
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac -= 2;
|
|
else
|
|
dma_c->ac += 2;
|
|
}
|
|
|
|
dma_stat_rq |= (1 << channel);
|
|
dma_c->cc--;
|
|
} while (dma_c->cc > 0);
|
|
|
|
ps2_cache_clean();
|
|
dma_stat |= (1 << channel);
|
|
break;
|
|
|
|
default: /*Memory verify*/
|
|
do {
|
|
if (! dma_c->size) {
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac--;
|
|
else
|
|
dma_c->ac++;
|
|
} else {
|
|
if (dma_c->ps2_mode & DMA_PS2_DEC2)
|
|
dma_c->ac -= 2;
|
|
else
|
|
dma_c->ac += 2;
|
|
}
|
|
|
|
dma_stat_rq |= (1 << channel);
|
|
dma->cc--;
|
|
} while (dma->cc > 0);
|
|
|
|
dma_stat |= (1 << channel);
|
|
break;
|
|
|
|
}
|
|
}
|
|
|
|
|
|
int
|
|
dma_mode(int channel)
|
|
{
|
|
return(dma[channel].mode);
|
|
}
|
|
|
|
|
|
/* DMA Bus Master Page Read/Write */
|
|
void
|
|
dma_bm_read(uint32_t PhysAddress, uint8_t *DataRead, uint32_t TotalSize, int TransferSize)
|
|
{
|
|
uint32_t i = 0, n, n2;
|
|
uint8_t bytes[4] = { 0, 0, 0, 0 };
|
|
|
|
n = TotalSize & ~(TransferSize - 1);
|
|
n2 = TotalSize - n;
|
|
|
|
/* Do the divisible block, if there is one. */
|
|
if (n) {
|
|
for (i = 0; i < n; i += TransferSize)
|
|
mem_read_phys((void *) &(DataRead[i]), PhysAddress + i, TransferSize);
|
|
}
|
|
|
|
/* Do the non-divisible block, if there is one. */
|
|
if (n2) {
|
|
mem_read_phys((void *) bytes, PhysAddress + n, TransferSize);
|
|
memcpy((void *) &(DataRead[n]), bytes, n2);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
dma_bm_write(uint32_t PhysAddress, const uint8_t *DataWrite, uint32_t TotalSize, int TransferSize)
|
|
{
|
|
uint32_t i = 0, n, n2;
|
|
uint8_t bytes[4] = { 0, 0, 0, 0 };
|
|
|
|
n = TotalSize & ~(TransferSize - 1);
|
|
n2 = TotalSize - n;
|
|
|
|
/* Do the divisible block, if there is one. */
|
|
if (n) {
|
|
for (i = 0; i < n; i += TransferSize)
|
|
mem_write_phys((void *) &(DataWrite[i]), PhysAddress + i, TransferSize);
|
|
}
|
|
|
|
/* Do the non-divisible block, if there is one. */
|
|
if (n2) {
|
|
mem_read_phys((void *) bytes, PhysAddress + n, TransferSize);
|
|
memcpy(bytes, (void *) &(DataWrite[n]), n2);
|
|
mem_write_phys((void *) bytes, PhysAddress + n, TransferSize);
|
|
}
|
|
}
|