0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
1382 lines
36 KiB
C
1382 lines
36 KiB
C
/*
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* VARCem Virtual ARchaeological Computer EMulator.
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* An emulator of (mostly) x86-based PC systems and devices,
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* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
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* spanning the era between 1981 and 1995.
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*
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* This file is part of the VARCem Project.
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*
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* Implementation of the PS/1 Model 2011 disk controller.
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*
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* XTA is the acronym for 'XT-Attached', which was basically
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* the XT-counterpart to what we know now as IDE (which is
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* also named ATA - AT Attachment.) The basic ideas was to
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* put the actual drive controller electronics onto the drive
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* itself, and have the host machine just talk to that using
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* a simpe, standardized I/O path- hence the name IDE, for
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* Integrated Drive Electronics.
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*
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* In the ATA version of IDE, the programming interface of
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* the IBM PC/AT (which used the Western Digitial 1002/1003
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* controllers) was kept, and, so, ATA-IDE assumes a 16bit
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* data path: it reads and writes 16bit words of data. The
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* disk drives for this bus commonly have an 'A' suffix to
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* identify them as 'ATBUS'.
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*
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* In XTA-IDE, which is slightly older, the programming
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* interface of the IBM PC/XT (which used the MFM controller
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* from Xebec) was kept, and, so, it uses an 8bit data path.
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* Disk drives for this bus commonly have the 'X' suffix to
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* mark them as being for this XTBUS variant.
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*
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* So, XTA and ATA try to do the same thing, but they use
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* different ways to achive their goal.
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*
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* Also, XTA is **not** the same as XTIDE. XTIDE is a modern
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* variant of ATA-IDE, but retro-fitted for use on 8bit XT
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* systems: an extra register is used to deal with the extra
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* data byte per transfer. XTIDE uses regular IDE drives,
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* and uses the regular ATA/IDE programming interface, just
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* with the extra register.
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*
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* NOTE: We should probably find a nicer way to integrate our Disk
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* Type table with the main code, so the user can only select
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* items from that list...
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*
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*
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*
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* Author: Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Based on my earlier HD20 driver for the EuroPC.
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* Thanks to Marco Bortolin for the help and feedback !!
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*
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* Copyright 2017-2019 Fred N. van Kempen.
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*
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* Redistribution and use in source and binary forms, with
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* or without modification, are permitted provided that the
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* following conditions are met:
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*
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* 1. Redistributions of source code must retain the entire
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* above notice, this list of conditions and the following
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* disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the
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* following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names
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* of its contributors may be used to endorse or promote
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* products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define __USE_LARGEFILE64
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#define _LARGEFILE_SOURCE
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#define _LARGEFILE64_SOURCE
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/dma.h>
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#include <86box/pic.h>
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#include <86box/device.h>
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#include <86box/hdc.h>
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#include <86box/hdd.h>
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#include <86box/plat.h>
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#include <86box/ui.h>
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#include <86box/machine.h>
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#define HDC_TIME (50*TIMER_USEC)
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#define HDC_TYPE_USER 47 /* user drive type */
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enum {
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STATE_IDLE = 0,
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STATE_RECV,
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STATE_RDATA,
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STATE_RDONE,
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STATE_SEND,
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STATE_SDATA,
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STATE_SDONE,
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STATE_FINIT,
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STATE_FDONE
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};
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|
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/* Command values. These deviate from the XTA ones. */
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#define CMD_READ_SECTORS 0x01 /* regular read-date */
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#define CMD_READ_VERIFY 0x02 /* read for verify, no data */
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#define CMD_READ_EXT 0x03 /* read extended (ecc) */
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#define CMD_READ_ID 0x05 /* read ID mark on cyl */
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#define CMD_RECALIBRATE 0x08 /* recalibrate to track0 */
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#define CMD_WRITE_SECTORS 0x09 /* regular write-data */
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#define CMD_WRITE_VERIFY 0x0a /* write-data with verify */
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#define CMD_WRITE_EXT 0x0b /* write extended (ecc) */
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#define CMD_FORMAT_DRIVE 0x0d /* format entire disk */
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#define CMD_SEEK 0x0e /* seek */
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#define CMD_FORMAT_TRACK 0x0f /* format one track */
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/* Attachment Status register (reg 2R) values (IBM PS/1 2011.) */
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#define ASR_TX_EN 0x01 /* transfer enable */
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#define ASR_INT_REQ 0x02 /* interrupt request */
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#define ASR_BUSY 0x04 /* busy */
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#define ASR_DIR 0x08 /* direction */
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#define ASR_DATA_REQ 0x10 /* data request */
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/* Attachment Control register (2W) values (IBM PS/1 2011.) */
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#define ACR_DMA_EN 0x01 /* DMA enable */
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#define ACR_INT_EN 0x02 /* interrupt enable */
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#define ACR_RESET 0x80 /* reset */
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/* Interrupt Status register (4R) values (IBM PS/1 2011.) */
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#define ISR_EQUIP_CHECK 0x01 /* internal hardware error */
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#define ISR_ERP_INVOKED 0x02 /* error recovery invoked */
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#define ISR_CMD_REJECT 0x20 /* command reject */
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#define ISR_INVALID_CMD 0x40 /* invalid command */
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#define ISR_TERMINATION 0x80 /* termination error */
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/* Attention register (4W) values (IBM PS/1 2011.) */
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#define ATT_DATA 0x10 /* data request */
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#define ATT_SSB 0x20 /* sense summary block */
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#define ATT_CSB 0x40 /* command specify block */
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#define ATT_CCB 0x80 /* command control block */
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/*
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* Define the Sense Summary Block.
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*
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* The sense summary block contains the current status of the
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* drive. The information in the summary block is updated after
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* each command is completed, after an error, or before the
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* block is transferred.
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*/
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#pragma pack(push,1)
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typedef struct {
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/* Status byte 0. */
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uint8_t track_0 :1, /* T0 */
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mbz1 :1, /* 0 */
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mbz2 :1, /* 0 */
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cylinder_err :1, /* CE */
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write_fault :1, /* WF */
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mbz3 :1, /* 0 */
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seek_end :1, /* SE */
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not_ready :1; /* NR */
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/* Status byte 1. */
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uint8_t id_not_found :1, /* ID */
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mbz4 :1, /* 0 */
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mbz5 :1, /* 0 */
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wrong_cyl :1, /* WC */
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all_bit_set :1, /* BT */
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mark_not_found :1, /* AM */
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ecc_crc_err :1, /* ET */
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ecc_crc_field :1; /* EF */
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/* Status byte 2. */
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uint8_t headsel_state :4, /* headsel state[4] */
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defective_sector:1, /* DS */
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retried_ok :1, /* RG */
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need_reset :1, /* RR */
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#if 1
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valid :1; /* 0 (abused as VALID) */
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#else
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mbz6 :1; /* 0 */
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#endif
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/* Most recent ID field seen. */
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uint8_t last_cyl_low; /* Cyl_Low[8] */
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uint8_t last_head :4, /* HD[4] */
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mbz7 :1, /* 0 */
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last_cyl_high :2, /* Cyl_high[2] */
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last_def_sect :1; /* DS */
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uint8_t last_sect; /* Sect[8] */
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uint8_t sect_size; /* Size[8] = 02 */
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/* Current position. */
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uint8_t curr_cyl_high :2, /* Cyl_High_[2] */
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mbz8 :1, /* 0 */
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mbz9 :1, /* 0 */
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curr_head :4; /* HD_2[4] */
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uint8_t curr_cyl_low; /* Cyl_Low_2[8] */
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uint8_t sect_corr; /* sectors corrected */
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uint8_t retries; /* retries */
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/*
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* This byte shows the progress of the controller through the
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* last command. It allows the system to monitor the controller
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* and determine if a reset is needed. When the transfer of the
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* control block is started, the value is set to hex 00. The
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* progress indicated by this byte is:
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*
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* 1. Set to hex 01 after the control block is successfully
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* transferred.
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*
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* 2. Set to hex 02 when the command is valid and the drive
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* is ready.
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*
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* 3. Set to hex 03 when the head is in the correct track.
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* The most-significant four bits (high nibble) are then
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* used to indicate the successful stages of the data
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* transfer:
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*
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* Bit 7 A sector was transferred between the system
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* and the sector buffer.
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*
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* Bit 6 A sector was transferred between the controller
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* and the sector buffer.
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*
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* Bit 5 An error was detected and error recovery
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* procedures have been started.
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*
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* Bit 4 The controller has completed the operation
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* and is now not busy.
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*
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* 4. When the transfer is complete, the low nibble equals hex 4
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* and the high nibble is unchanged.
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*/
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uint8_t cmd_syndrome; /* command syndrome */
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uint8_t drive_type; /* drive type */
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uint8_t rsvd; /* reserved byte */
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} ssb_t;
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#pragma pack(pop)
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/*
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* Define the Format Control Block.
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*
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* The format control block (FCB) specifies the ID data used
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* in formatting the track. It is used by the Format Track
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* and Format Disk commands and contains five bytes for each
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* sector formatted on that track.
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*
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* When the Format Disk command is used, the control block
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* contains the sector information of all sectors for head 0,
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* cylinder 0. The drive will use the same block to format
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* the rest of the disk and automatically increment the head
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* number and cylinder number for the remaining tracks. The
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* sector numbers, sector size, and the fill byte will be
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* the same for each track.
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*
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* The drive formats the sector IDs on the disk in the same
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* order as they are specified in the control block.
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* Therefore, sector interleaving is accomplished by filling
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* in the control block with the desired interleave.
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*
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* For example, when formatting 17 sectors per track with an
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* interleave of 2, the control block has the first 5 bytes
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* with a sector number of 1, the second with a sector number
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* of 10, the third with a sector number of 2, and continuing
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* until all 17 sectors for that track are defined.
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*
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* The format for the format control block is described in
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* the following. The five bytes are repeated for each
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* sector on the track. The control block must contain an
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* even number of bytes. If an odd number of sectors are
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* being formatted, an additional byte is sent with all
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* bits 0.
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*/
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#pragma pack(push,1)
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typedef struct {
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uint8_t cyl_high :2, /* cylinder [9:8] bits */
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defective_sector:1, /* DS */
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mbz1 :1, /* 0 */
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head :4; /* head number */
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uint8_t cyl_low; /* cylinder [7:0] bits */
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uint8_t sector; /* sector number */
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uint8_t mbz2 :1, /* 0 */
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mbo :1, /* 1 */
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mbz3 :6; /* 000000 */
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uint8_t fill; /* filler byte */
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} fcb_t;
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#pragma pack(pop)
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/*
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* Define the Command Control Block.
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*
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* The system specifies the operation by sending the 6-byte
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* command control block to the controller. It can be sent
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* through a DMA or PIO operation.
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*/
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#pragma pack(push,1)
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typedef struct {
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uint8_t ec_p :1, /* EC/P (ecc/park) */
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mbz1 :1, /* 0 */
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auto_seek :1, /* AS (auto-seek) */
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no_data :1, /* ND (no data) */
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cmd :4; /* command code[4] */
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uint8_t cyl_high :2, /* cylinder [9:8] bits */
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mbz2 :2, /* 00 */
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head :4; /* head number */
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uint8_t cyl_low; /* cylinder [7:0] bits */
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uint8_t sector; /* sector number */
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uint8_t mbz3 :1, /* 0 */
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mbo1 :1, /* 1 */
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mbz4 :6; /* 000000 */
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uint8_t count; /* blk count/interleave */
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} ccb_t;
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#pragma pack(pop)
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/* Define the hard drive geometry table. */
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typedef struct {
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uint16_t cyl;
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uint8_t hpc;
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uint8_t spt;
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int16_t wpc;
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int16_t lz;
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} geom_t;
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/* Define an attached drive. */
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typedef struct {
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int8_t id, /* drive ID on bus */
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present, /* drive is present */
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hdd_num, /* index to global disk table */
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type; /* drive type ID */
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uint16_t cur_cyl; /* last known position of heads */
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uint8_t spt, /* active drive parameters */
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hpc;
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uint16_t tracks;
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uint8_t cfg_spt, /* configured drive parameters */
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cfg_hpc;
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uint16_t cfg_tracks;
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} drive_t;
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|
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typedef struct {
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uint16_t base; /* controller base I/O address */
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int8_t irq; /* controller IRQ channel */
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int8_t dma; /* controller DMA channel */
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|
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/* Registers. */
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uint8_t attn, /* ATTENTION register */
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ctrl, /* Control register (ACR) */
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status, /* Status register (ASR) */
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intstat; /* Interrupt Status register (ISR) */
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|
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uint8_t *reg_91; /* handle to system board's register 0x91 */
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|
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/* Controller state. */
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uint64_t callback;
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pc_timer_t timer;
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int8_t state, /* controller state */
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reset; /* reset state counter */
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|
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/* Data transfer. */
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int16_t buf_idx, /* buffer index and pointer */
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buf_len;
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uint8_t *buf_ptr;
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|
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/* Current operation parameters. */
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ssb_t ssb; /* sense block */
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ccb_t ccb; /* command control block */
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uint16_t track; /* requested track# */
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uint8_t head, /* requested head# */
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sector; /* requested sector# */
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int count; /* requested sector count */
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|
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drive_t drives[XTA_NUM]; /* the attached drive(s) */
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|
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uint8_t data[512]; /* data buffer */
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uint8_t sector_buf[512]; /* sector buffer */
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} hdc_t;
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|
|
|
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/*
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* IBM hard drive types 1-44.
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*
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* We need these to translate the selected disk's
|
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* geometry back to a valid type through the SSB.
|
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*
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* Cyl. Head Sect. Write Land
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* p-comp Zone
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*/
|
|
static const geom_t ibm_type_table[] = {
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{ 0, 0, 0, 0, 0 }, /* 0 (none) */
|
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{ 306, 4, 17, 128, 305 }, /* 1 10 MB */
|
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{ 615, 4, 17, 300, 615 }, /* 2 20 MB */
|
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{ 615, 6, 17, 300, 615 }, /* 3 31 MB */
|
|
{ 940, 8, 17, 512, 940 }, /* 4 62 MB */
|
|
{ 940, 6, 17, 512, 940 }, /* 5 47 MB */
|
|
{ 615, 4, 17, -1, 615 }, /* 6 20 MB */
|
|
{ 462, 8, 17, 256, 511 }, /* 7 31 MB */
|
|
{ 733, 5, 17, -1, 733 }, /* 8 30 MB */
|
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{ 900, 15, 17, -1, 901 }, /* 9 112 MB */
|
|
{ 820, 3, 17, -1, 820 }, /* 10 20 MB */
|
|
{ 855, 5, 17, -1, 855 }, /* 11 35 MB */
|
|
{ 855, 7, 17, -1, 855 }, /* 12 50 MB */
|
|
{ 306, 8, 17, 128, 319 }, /* 13 20 MB */
|
|
{ 733, 7, 17, -1, 733 }, /* 14 43 MB */
|
|
{ 0, 0, 0, 0, 0 }, /* 15 (rsvd) */
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{ 612, 4, 17, 0, 663 }, /* 16 20 MB */
|
|
{ 977, 5, 17, 300, 977 }, /* 17 41 MB */
|
|
{ 977, 7, 17, -1, 977 }, /* 18 57 MB */
|
|
{ 1024, 7, 17, 512, 1023 }, /* 19 59 MB */
|
|
{ 733, 5, 17, 300, 732 }, /* 20 30 MB */
|
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{ 733, 7, 17, 300, 732 }, /* 21 43 MB */
|
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{ 733, 5, 17, 300, 733 }, /* 22 30 MB */
|
|
{ 306, 4, 17, 0, 336 }, /* 23 10 MB */
|
|
{ 612, 4, 17, 305, 663 }, /* 24 20 MB */
|
|
{ 306, 4, 17, -1, 340 }, /* 25 10 MB */
|
|
{ 612, 4, 17, -1, 670 }, /* 26 20 MB */
|
|
{ 698, 7, 17, 300, 732 }, /* 27 41 MB */
|
|
{ 976, 5, 17, 488, 977 }, /* 28 40 MB */
|
|
{ 306, 4, 17, 0, 340 }, /* 29 10 MB */
|
|
{ 611, 4, 17, 306, 663 }, /* 30 20 MB */
|
|
{ 732, 7, 17, 300, 732 }, /* 31 43 MB */
|
|
{ 1023, 5, 17, -1, 1023 }, /* 32 42 MB */
|
|
{ 614, 4, 25, -1, 663 }, /* 33 30 MB */
|
|
{ 775, 2, 27, -1, 900 }, /* 34 20 MB */
|
|
{ 921, 2, 33, -1, 1000 }, /* 35 30 MB * */
|
|
{ 402, 4, 26, -1, 460 }, /* 36 20 MB */
|
|
{ 580, 6, 26, -1, 640 }, /* 37 44 MB */
|
|
{ 845, 2, 36, -1, 1023 }, /* 38 30 MB * */
|
|
{ 769, 3, 36, -1, 1023 }, /* 39 41 MB * */
|
|
{ 531, 4, 39, -1, 532 }, /* 40 40 MB */
|
|
{ 577, 2, 36, -1, 1023 }, /* 41 20 MB */
|
|
{ 654, 2, 32, -1, 674 }, /* 42 20 MB */
|
|
{ 923, 5, 36, -1, 1023 }, /* 43 81 MB */
|
|
{ 531, 8, 39, -1, 532 } /* 44 81 MB */
|
|
};
|
|
|
|
|
|
#ifdef ENABLE_PS1_HDC_LOG
|
|
int ps1_hdc_do_log = ENABLE_PS1_HDC_LOG;
|
|
|
|
|
|
static void
|
|
ps1_hdc_log(const char *fmt, ...)
|
|
{
|
|
va_list ap;
|
|
|
|
if (ps1_hdc_do_log)
|
|
{
|
|
va_start(ap, fmt);
|
|
pclog_ex(fmt, ap);
|
|
va_end(ap);
|
|
}
|
|
}
|
|
#else
|
|
#define ps1_hdc_log(fmt, ...)
|
|
#endif
|
|
|
|
static void
|
|
hdc_set_callback(hdc_t *dev, uint64_t callback)
|
|
{
|
|
if (!dev) {
|
|
return;
|
|
}
|
|
|
|
if (callback) {
|
|
dev->callback = callback;
|
|
timer_set_delay_u64(&dev->timer, dev->callback);
|
|
} else {
|
|
dev->callback = 0;
|
|
timer_disable(&dev->timer);
|
|
}
|
|
}
|
|
|
|
/* FIXME: we should use the disk/hdd_table.c code with custom tables! */
|
|
static int
|
|
ibm_drive_type(drive_t *drive)
|
|
{
|
|
const geom_t *ptr;
|
|
int i;
|
|
|
|
for (i = 0; i < (sizeof(ibm_type_table) / sizeof(geom_t)); i++) {
|
|
ptr = &ibm_type_table[i];
|
|
if ((drive->tracks == ptr->cyl) &&
|
|
(drive->hpc == ptr->hpc) && (drive->spt == ptr->spt)) return(i);
|
|
}
|
|
|
|
return(HDC_TYPE_USER);
|
|
}
|
|
|
|
|
|
static void
|
|
set_intr(hdc_t *dev, int raise)
|
|
{
|
|
if (raise) {
|
|
dev->status |= ASR_INT_REQ;
|
|
if (dev->ctrl & ACR_INT_EN)
|
|
picint(1 << dev->irq);
|
|
} else {
|
|
dev->status &= ~ASR_INT_REQ;
|
|
picintc(1 << dev->irq);
|
|
}
|
|
}
|
|
|
|
|
|
/* Get the logical (block) address of a CHS triplet. */
|
|
static int
|
|
get_sector(hdc_t *dev, drive_t *drive, off64_t *addr)
|
|
{
|
|
if (drive->cur_cyl != dev->track) {
|
|
ps1_hdc_log("HDC: get_sector: wrong cylinder %d/%d\n",
|
|
drive->cur_cyl, dev->track);
|
|
dev->ssb.wrong_cyl = 1;
|
|
return(1);
|
|
}
|
|
|
|
if (dev->head >= drive->hpc) {
|
|
ps1_hdc_log("HDC: get_sector: past end of heads\n");
|
|
dev->ssb.cylinder_err = 1;
|
|
return(1);
|
|
}
|
|
|
|
if (dev->sector > drive->spt) {
|
|
ps1_hdc_log("HDC: get_sector: past end of sectors\n");
|
|
dev->ssb.mark_not_found = 1;
|
|
return(1);
|
|
}
|
|
|
|
/* Calculate logical address (block number) of desired sector. */
|
|
*addr = ((((off64_t) dev->track*drive->hpc) + \
|
|
dev->head)*drive->spt) + dev->sector - 1;
|
|
|
|
return(0);
|
|
}
|
|
|
|
|
|
static void
|
|
next_sector(hdc_t *dev, drive_t *drive)
|
|
{
|
|
if (++dev->sector > drive->spt) {
|
|
dev->sector = 1;
|
|
if (++dev->head >= drive->hpc) {
|
|
dev->head = 0;
|
|
dev->track++;
|
|
if (++drive->cur_cyl >= drive->tracks) {
|
|
drive->cur_cyl = drive->tracks-1;
|
|
dev->ssb.cylinder_err = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* Finish up. Repeated all over, so a function it is now. */
|
|
static void
|
|
do_finish(hdc_t *dev)
|
|
{
|
|
dev->state = STATE_IDLE;
|
|
|
|
dev->attn &= ~(ATT_CCB | ATT_DATA);
|
|
|
|
dev->status = 0x00;
|
|
|
|
set_intr(dev, 1);
|
|
}
|
|
|
|
|
|
/* Seek to a cylinder. */
|
|
static int
|
|
do_seek(hdc_t *dev, drive_t *drive, uint16_t cyl)
|
|
{
|
|
if (cyl >= drive->tracks) {
|
|
dev->ssb.cylinder_err = 1;
|
|
return(1);
|
|
}
|
|
|
|
dev->track = cyl;
|
|
drive->cur_cyl = dev->track;
|
|
|
|
return(0);
|
|
}
|
|
|
|
|
|
/* Format a track or an entire drive. */
|
|
static void
|
|
do_format(hdc_t *dev, drive_t *drive, ccb_t *ccb)
|
|
{
|
|
int start_cyl, end_cyl;
|
|
int intr = 0, val;
|
|
off64_t addr;
|
|
#if 0
|
|
fcb_t *fcb;
|
|
#endif
|
|
|
|
/* Get the parameters from the CCB. */
|
|
if (ccb->cmd == CMD_FORMAT_DRIVE) {
|
|
start_cyl = 0;
|
|
end_cyl = drive->tracks;
|
|
} else {
|
|
start_cyl = (ccb->cyl_low | (ccb->cyl_high << 8));
|
|
end_cyl = start_cyl + 1;
|
|
}
|
|
|
|
switch (dev->state) {
|
|
case STATE_IDLE:
|
|
/* Ready to transfer the FCB data in. */
|
|
dev->state = STATE_RDATA;
|
|
dev->buf_idx = 0;
|
|
dev->buf_ptr = dev->data;
|
|
dev->buf_len = ccb->count * sizeof(fcb_t);
|
|
if (dev->buf_len & 1)
|
|
dev->buf_len++; /* must be even */
|
|
|
|
/* Enable for PIO or DMA, as needed. */
|
|
#if NOT_USED
|
|
if (dev->ctrl & ACR_DMA_EN)
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
else
|
|
#endif
|
|
dev->status |= ASR_DATA_REQ;
|
|
break;
|
|
|
|
case STATE_RDATA:
|
|
/* Perform DMA. */
|
|
while (dev->buf_idx < dev->buf_len) {
|
|
val = dma_channel_read(dev->dma);
|
|
if (val == DMA_NODATA) {
|
|
dev->intstat |= ISR_EQUIP_CHECK;
|
|
dev->ssb.need_reset = 1;
|
|
intr = 1;
|
|
break;
|
|
}
|
|
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
|
|
dev->buf_idx++;
|
|
}
|
|
dev->state = STATE_RDONE;
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
break;
|
|
|
|
case STATE_RDONE:
|
|
if (! (dev->ctrl & ACR_DMA_EN))
|
|
dev->status &= ~ASR_DATA_REQ;
|
|
|
|
/* Point to the FCB we got. */
|
|
#if 0
|
|
fcb = (fcb_t *)dev->data;
|
|
#endif
|
|
dev->state = STATE_FINIT;
|
|
/*FALLTHROUGH*/
|
|
|
|
case STATE_FINIT:
|
|
do_fmt:
|
|
/* Activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 1);
|
|
|
|
/* Seek to cylinder. */
|
|
if (do_seek(dev, drive, start_cyl)) {
|
|
intr = 1;
|
|
break;
|
|
}
|
|
dev->head = ccb->head;
|
|
dev->sector = 1;
|
|
|
|
/* Get address of sector to write. */
|
|
if (get_sector(dev, drive, &addr)) {
|
|
intr = 1;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* For now, we don't use the info from
|
|
* the FCB, although we should at least
|
|
* use it's "filler byte" value...
|
|
*/
|
|
#if 0
|
|
hdd_image_zero_ex(drive->hdd_num, addr, fcb->fill, drive->spt);
|
|
#else
|
|
hdd_image_zero(drive->hdd_num, addr, drive->spt);
|
|
#endif
|
|
|
|
/* Done with this track. */
|
|
dev->state = STATE_FDONE;
|
|
/*FALLTHROUGH*/
|
|
|
|
case STATE_FDONE:
|
|
/* One more track done. */
|
|
if (++start_cyl == end_cyl) {
|
|
intr = 1;
|
|
break;
|
|
}
|
|
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
/* This saves us a LOT of code. */
|
|
dev->state = STATE_FINIT;
|
|
goto do_fmt;
|
|
}
|
|
|
|
/* If we errored out, go back idle. */
|
|
if (intr) {
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
do_finish(dev);
|
|
}
|
|
}
|
|
|
|
|
|
/* Execute the CCB we just received. */
|
|
static void
|
|
hdc_callback(void *priv)
|
|
{
|
|
hdc_t *dev = (hdc_t *)priv;
|
|
ccb_t *ccb = &dev->ccb;
|
|
drive_t *drive;
|
|
off64_t addr;
|
|
int no_data = 0;
|
|
int val;
|
|
|
|
/* Cancel timer. */
|
|
dev->callback = 0;
|
|
|
|
/* Clear the SSB error bits. */
|
|
dev->ssb.track_0 = 0;
|
|
dev->ssb.cylinder_err = 0;
|
|
dev->ssb.write_fault = 0;
|
|
dev->ssb.seek_end = 0;
|
|
dev->ssb.not_ready = 0;
|
|
dev->ssb.id_not_found = 0;
|
|
dev->ssb.wrong_cyl = 0;
|
|
dev->ssb.all_bit_set = 0;
|
|
dev->ssb.mark_not_found = 0;
|
|
dev->ssb.ecc_crc_err = 0;
|
|
dev->ssb.ecc_crc_field = 0;
|
|
dev->ssb.valid = 1;
|
|
|
|
/* We really only support one drive, but ohwell. */
|
|
drive = &dev->drives[0];
|
|
|
|
switch (ccb->cmd) {
|
|
case CMD_READ_VERIFY:
|
|
no_data = 1;
|
|
/*FALLTHROUGH*/
|
|
|
|
case CMD_READ_SECTORS:
|
|
if (! drive->present) {
|
|
dev->ssb.not_ready = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
switch (dev->state) {
|
|
case STATE_IDLE:
|
|
/* Seek to cylinder if requested. */
|
|
if (ccb->auto_seek) {
|
|
if (do_seek(dev, drive,
|
|
(ccb->cyl_low|(ccb->cyl_high<<8)))) {
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
}
|
|
dev->head = ccb->head;
|
|
dev->sector = ccb->sector;
|
|
|
|
/* Get sector count and size. */
|
|
dev->count = (int)ccb->count;
|
|
dev->buf_len = (128 << dev->ssb.sect_size);
|
|
|
|
dev->state = STATE_SEND;
|
|
/*FALLTHROUGH*/
|
|
|
|
case STATE_SEND:
|
|
/* Activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 1);
|
|
|
|
do_send:
|
|
/* Get address of sector to load. */
|
|
if (get_sector(dev, drive, &addr)) {
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
/* Read the block from the image. */
|
|
hdd_image_read(drive->hdd_num, addr, 1,
|
|
(uint8_t *)dev->sector_buf);
|
|
|
|
/* Ready to transfer the data out. */
|
|
dev->state = STATE_SDATA;
|
|
dev->buf_idx = 0;
|
|
if (no_data) {
|
|
/* Delay a bit, no actual transfer. */
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
} else {
|
|
if (dev->ctrl & ACR_DMA_EN) {
|
|
/* DMA enabled. */
|
|
dev->buf_ptr = dev->sector_buf;
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
} else {
|
|
/* No DMA, do PIO. */
|
|
dev->status |= (ASR_DATA_REQ|ASR_DIR);
|
|
|
|
/* Copy from sector to data. */
|
|
memcpy(dev->data,
|
|
dev->sector_buf,
|
|
dev->buf_len);
|
|
dev->buf_ptr = dev->data;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case STATE_SDATA:
|
|
if (! no_data) {
|
|
/* Perform DMA. */
|
|
while (dev->buf_idx < dev->buf_len) {
|
|
val = dma_channel_write(dev->dma,
|
|
*dev->buf_ptr++);
|
|
if (val == DMA_NODATA) {
|
|
ps1_hdc_log("HDC: CMD_READ_SECTORS out of data (idx=%d, len=%d)!\n", dev->buf_idx, dev->buf_len);
|
|
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
dev->intstat |= ISR_EQUIP_CHECK;
|
|
dev->ssb.need_reset = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
dev->buf_idx++;
|
|
}
|
|
}
|
|
dev->state = STATE_SDONE;
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
break;
|
|
|
|
case STATE_SDONE:
|
|
dev->buf_idx = 0;
|
|
if (--dev->count == 0) {
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
if (! (dev->ctrl & ACR_DMA_EN))
|
|
dev->status &= ~(ASR_DATA_REQ|ASR_DIR);
|
|
dev->ssb.cmd_syndrome = 0xD4;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
/* Addvance to next sector. */
|
|
next_sector(dev, drive);
|
|
|
|
/* This saves us a LOT of code. */
|
|
dev->state = STATE_SEND;
|
|
goto do_send;
|
|
}
|
|
break;
|
|
|
|
case CMD_READ_EXT: /* READ_EXT */
|
|
case CMD_READ_ID: /* READ_ID */
|
|
if (! drive->present) {
|
|
dev->ssb.not_ready = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
dev->intstat |= ISR_INVALID_CMD;
|
|
do_finish(dev);
|
|
break;
|
|
|
|
case CMD_RECALIBRATE: /* RECALIBRATE */
|
|
if (drive->present) {
|
|
dev->track = drive->cur_cyl = 0;
|
|
} else {
|
|
dev->ssb.not_ready = 1;
|
|
dev->intstat |= ISR_TERMINATION;
|
|
}
|
|
|
|
do_finish(dev);
|
|
break;
|
|
|
|
case CMD_WRITE_VERIFY:
|
|
no_data = 1;
|
|
/*FALLTHROUGH*/
|
|
|
|
case CMD_WRITE_SECTORS:
|
|
if (! drive->present) {
|
|
dev->ssb.not_ready = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
switch (dev->state) {
|
|
case STATE_IDLE:
|
|
/* Seek to cylinder if requested. */
|
|
if (ccb->auto_seek) {
|
|
if (do_seek(dev, drive,
|
|
(ccb->cyl_low|(ccb->cyl_high<<8)))) {
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
}
|
|
dev->head = ccb->head;
|
|
dev->sector = ccb->sector;
|
|
|
|
/* Get sector count and size. */
|
|
dev->count = (int)ccb->count;
|
|
dev->buf_len = (128 << dev->ssb.sect_size);
|
|
|
|
dev->state = STATE_RECV;
|
|
/*FALLTHROUGH*/
|
|
|
|
case STATE_RECV:
|
|
/* Activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 1);
|
|
do_recv:
|
|
/* Ready to transfer the data in. */
|
|
dev->state = STATE_RDATA;
|
|
dev->buf_idx = 0;
|
|
if (no_data) {
|
|
/* Delay a bit, no actual transfer. */
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
} else {
|
|
if (dev->ctrl & ACR_DMA_EN) {
|
|
/* DMA enabled. */
|
|
dev->buf_ptr = dev->sector_buf;
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
} else {
|
|
/* No DMA, do PIO. */
|
|
dev->buf_ptr = dev->data;
|
|
dev->status |= ASR_DATA_REQ;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case STATE_RDATA:
|
|
if (! no_data) {
|
|
/* Perform DMA. */
|
|
while (dev->buf_idx < dev->buf_len) {
|
|
val = dma_channel_read(dev->dma);
|
|
if (val == DMA_NODATA) {
|
|
ps1_hdc_log("HDC: CMD_WRITE_SECTORS out of data (idx=%d, len=%d)!\n", dev->buf_idx, dev->buf_len);
|
|
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
dev->intstat |= ISR_EQUIP_CHECK;
|
|
dev->ssb.need_reset = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
|
|
dev->buf_idx++;
|
|
}
|
|
}
|
|
dev->state = STATE_RDONE;
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
break;
|
|
|
|
case STATE_RDONE:
|
|
/* Copy from data to sector if PIO. */
|
|
if (! (dev->ctrl & ACR_DMA_EN))
|
|
memcpy(dev->sector_buf,
|
|
dev->data,
|
|
dev->buf_len);
|
|
|
|
/* Get address of sector to write. */
|
|
if (get_sector(dev, drive, &addr)) {
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
/* Write the block to the image. */
|
|
hdd_image_write(drive->hdd_num, addr, 1,
|
|
(uint8_t *)dev->sector_buf);
|
|
|
|
dev->buf_idx = 0;
|
|
if (--dev->count == 0) {
|
|
/* De-activate the status icon. */
|
|
ui_sb_update_icon(SB_HDD|HDD_BUS_XTA, 0);
|
|
|
|
if (! (dev->ctrl & ACR_DMA_EN))
|
|
dev->status &= ~ASR_DATA_REQ;
|
|
dev->ssb.cmd_syndrome = 0xD4;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
/* Advance to next sector. */
|
|
next_sector(dev, drive);
|
|
|
|
/* This saves us a LOT of code. */
|
|
dev->state = STATE_RECV;
|
|
goto do_recv;
|
|
}
|
|
break;
|
|
|
|
case CMD_FORMAT_DRIVE:
|
|
case CMD_FORMAT_TRACK:
|
|
do_format(dev, drive, ccb);
|
|
break;
|
|
|
|
case CMD_SEEK:
|
|
if (! drive->present) {
|
|
dev->ssb.not_ready = 1;
|
|
do_finish(dev);
|
|
return;
|
|
}
|
|
|
|
if (ccb->ec_p == 1) {
|
|
/* Park the heads. */
|
|
val = do_seek(dev, drive, drive->tracks-1);
|
|
} else {
|
|
/* Seek to cylinder. */
|
|
val = do_seek(dev, drive,
|
|
(ccb->cyl_low|(ccb->cyl_high<<8)));
|
|
}
|
|
if (! val)
|
|
dev->ssb.seek_end = 1;
|
|
do_finish(dev);
|
|
break;
|
|
|
|
default:
|
|
dev->intstat |= ISR_INVALID_CMD;
|
|
do_finish(dev);
|
|
}
|
|
}
|
|
|
|
|
|
/* Prepare to send the SSB block. */
|
|
static void
|
|
hdc_send_ssb(hdc_t *dev)
|
|
{
|
|
drive_t *drive;
|
|
|
|
/* We only support one drive, really, but ohwell. */
|
|
drive = &dev->drives[0];
|
|
|
|
if (! dev->ssb.valid) {
|
|
/* Create a valid SSB. */
|
|
memset(&dev->ssb, 0x00, sizeof(dev->ssb));
|
|
dev->ssb.sect_size = 0x02; /* 512 bytes */
|
|
dev->ssb.drive_type = drive->type;
|
|
}
|
|
|
|
/* Update position fields. */
|
|
dev->ssb.track_0 = !!(dev->track == 0);
|
|
dev->ssb.last_cyl_low = dev->ssb.curr_cyl_low;
|
|
dev->ssb.last_cyl_high = dev->ssb.curr_cyl_high;
|
|
dev->ssb.last_head = dev->ssb.curr_head;
|
|
dev->ssb.curr_cyl_high = ((dev->track >> 8) & 0x03);
|
|
dev->ssb.curr_cyl_low = (dev->track & 0xff);
|
|
dev->ssb.curr_head = (dev->head & 0x0f);
|
|
|
|
dev->ssb.headsel_state = dev->ssb.curr_head;
|
|
dev->ssb.last_sect = dev->sector;
|
|
|
|
/* We abuse an unused MBZ bit, so clear it. */
|
|
dev->ssb.valid = 0;
|
|
|
|
/* Set up the transfer buffer for the SSB. */
|
|
dev->buf_idx = 0;
|
|
dev->buf_len = sizeof(dev->ssb);
|
|
dev->buf_ptr = (uint8_t *)&dev->ssb;
|
|
|
|
/* Done with the SSB. */
|
|
dev->attn &= ~ATT_SSB;
|
|
}
|
|
|
|
|
|
/* Read one of the controller registers. */
|
|
static uint8_t
|
|
hdc_read(uint16_t port, void *priv)
|
|
{
|
|
hdc_t *dev = (hdc_t *)priv;
|
|
uint8_t ret = 0xff;
|
|
|
|
/* TRM: tell system board we are alive. */
|
|
*dev->reg_91 |= 0x01;
|
|
|
|
switch (port & 7) {
|
|
case 0: /* DATA register */
|
|
if (dev->state == STATE_SDATA) {
|
|
if (dev->buf_idx > dev->buf_len) {
|
|
ps1_hdc_log("HDC: read with empty buffer!\n");
|
|
dev->state = STATE_IDLE;
|
|
dev->intstat |= ISR_INVALID_CMD;
|
|
dev->status &= (ASR_TX_EN|ASR_DATA_REQ|ASR_DIR);
|
|
set_intr(dev, 1);
|
|
break;
|
|
}
|
|
|
|
ret = dev->buf_ptr[dev->buf_idx];
|
|
if (++dev->buf_idx == dev->buf_len) {
|
|
/* Data block sent OK. */
|
|
dev->status &= ~(ASR_TX_EN|ASR_DATA_REQ|ASR_DIR);
|
|
dev->state = STATE_IDLE;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 2: /* ASR */
|
|
ret = dev->status;
|
|
break;
|
|
|
|
case 4: /* ISR */
|
|
ret = dev->intstat;
|
|
dev->intstat = 0x00;
|
|
break;
|
|
}
|
|
|
|
return(ret);
|
|
}
|
|
|
|
|
|
static void
|
|
hdc_write(uint16_t port, uint8_t val, void *priv)
|
|
{
|
|
hdc_t *dev = (hdc_t *)priv;
|
|
|
|
/* TRM: tell system board we are alive. */
|
|
*dev->reg_91 |= 0x01;
|
|
|
|
switch (port & 7) {
|
|
case 0: /* DATA register */
|
|
if (dev->state == STATE_RDATA) {
|
|
if (dev->buf_idx >= dev->buf_len) {
|
|
ps1_hdc_log("HDC: write with full buffer!\n");
|
|
dev->intstat |= ISR_INVALID_CMD;
|
|
dev->status &= ~ASR_DATA_REQ;
|
|
set_intr(dev, 1);
|
|
break;
|
|
}
|
|
|
|
/* Store the data into the buffer. */
|
|
dev->buf_ptr[dev->buf_idx] = val;
|
|
if (++dev->buf_idx == dev->buf_len) {
|
|
/* We got all the data we need. */
|
|
dev->status &= ~ASR_DATA_REQ;
|
|
dev->state = STATE_IDLE;
|
|
|
|
/* If we were receiving a CCB, execute it. */
|
|
if (dev->attn & ATT_CCB) {
|
|
/*
|
|
* If we were already busy with
|
|
* a CCB, then it must have had
|
|
* some new data using PIO.
|
|
*/
|
|
if (dev->status & ASR_BUSY)
|
|
dev->state = STATE_RDONE;
|
|
else
|
|
dev->status |= ASR_BUSY;
|
|
|
|
/* Schedule command execution. */
|
|
hdc_set_callback(dev, HDC_TIME);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 2: /* ACR */
|
|
dev->ctrl = val;
|
|
if (val & ACR_INT_EN)
|
|
set_intr(dev, 0); /* clear IRQ */
|
|
|
|
if (dev->reset != 0) {
|
|
if (++dev->reset == 3) {
|
|
dev->reset = 0;
|
|
|
|
set_intr(dev, 1);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (val & ACR_RESET)
|
|
dev->reset = 1;
|
|
break;
|
|
|
|
case 4: /* ATTN */
|
|
dev->status &= ~ASR_INT_REQ;
|
|
if (val & ATT_DATA) {
|
|
/* Dunno. Start PIO/DMA now? */
|
|
}
|
|
|
|
if (val & ATT_SSB) {
|
|
if (dev->attn & ATT_CCB) {
|
|
/* Hey now, we're still busy for you! */
|
|
dev->intstat |= ISR_INVALID_CMD;
|
|
set_intr(dev, 1);
|
|
break;
|
|
}
|
|
|
|
/* OK, prepare for sending an SSB. */
|
|
dev->attn |= ATT_SSB;
|
|
|
|
/* Grab or initialize an SSB to send. */
|
|
hdc_send_ssb(dev);
|
|
|
|
dev->state = STATE_SDATA;
|
|
dev->status |= (ASR_TX_EN|ASR_DATA_REQ|ASR_DIR);
|
|
set_intr(dev, 1);
|
|
}
|
|
|
|
if (val & ATT_CCB) {
|
|
dev->attn |= ATT_CCB;
|
|
|
|
/* Set up the transfer buffer for a CCB. */
|
|
dev->buf_idx = 0;
|
|
dev->buf_len = sizeof(dev->ccb);
|
|
dev->buf_ptr = (uint8_t *)&dev->ccb;
|
|
|
|
dev->state = STATE_RDATA;
|
|
dev->status |= ASR_DATA_REQ;
|
|
set_intr(dev, 1);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
static void *
|
|
ps1_hdc_init(const device_t *info)
|
|
{
|
|
drive_t *drive;
|
|
hdc_t *dev;
|
|
int c, i;
|
|
|
|
/* Allocate and initialize device block. */
|
|
dev = malloc(sizeof(hdc_t));
|
|
memset(dev, 0x00, sizeof(hdc_t));
|
|
|
|
/* Set up controller parameters for PS/1 2011. */
|
|
dev->base = 0x0320;
|
|
dev->irq = 14;
|
|
dev->dma = 3;
|
|
|
|
ps1_hdc_log("HDC: initializing (I/O=%04X, IRQ=%d, DMA=%d)\n",
|
|
dev->base, dev->irq, dev->dma);
|
|
|
|
/* Load any disks for this device class. */
|
|
c = 0;
|
|
for (i = 0; i < HDD_NUM; i++) {
|
|
if ((hdd[i].bus == HDD_BUS_XTA) && (hdd[i].xta_channel < 1)) {
|
|
drive = &dev->drives[hdd[i].xta_channel];
|
|
|
|
if (! hdd_image_load(i)) {
|
|
drive->present = 0;
|
|
continue;
|
|
}
|
|
drive->id = c;
|
|
|
|
/* These are the "hardware" parameters (from the image.) */
|
|
drive->cfg_spt = (uint8_t)(hdd[i].spt & 0xff);
|
|
drive->cfg_hpc = (uint8_t)(hdd[i].hpc & 0xff);
|
|
drive->cfg_tracks = (uint16_t)hdd[i].tracks;
|
|
|
|
/* Use them as "active" parameters until overwritten. */
|
|
drive->spt = drive->cfg_spt;
|
|
drive->hpc = drive->cfg_hpc;
|
|
drive->tracks = drive->cfg_tracks;
|
|
|
|
drive->type = ibm_drive_type(drive);
|
|
drive->hdd_num = i;
|
|
drive->present = 1;
|
|
|
|
ps1_hdc_log("HDC: drive%d (type %d: cyl=%d,hd=%d,spt=%d), disk %d\n",
|
|
hdd[i].xta_channel, drive->type,
|
|
drive->tracks, drive->hpc, drive->spt, i);
|
|
|
|
if (++c > 1) break;
|
|
}
|
|
}
|
|
|
|
/* Sectors are 1-based. */
|
|
dev->sector = 1;
|
|
|
|
/* Enable the I/O block. */
|
|
io_sethandler(dev->base, 5,
|
|
hdc_read,NULL,NULL, hdc_write,NULL,NULL, dev);
|
|
|
|
/* Create a timer for command delays. */
|
|
timer_add(&dev->timer, hdc_callback, dev, 0);
|
|
|
|
return(dev);
|
|
}
|
|
|
|
|
|
static void
|
|
ps1_hdc_close(void *priv)
|
|
{
|
|
hdc_t *dev = (hdc_t *)priv;
|
|
drive_t *drive;
|
|
int d;
|
|
|
|
/* Remove the I/O handler. */
|
|
io_removehandler(dev->base, 5,
|
|
hdc_read,NULL,NULL, hdc_write,NULL,NULL, dev);
|
|
|
|
/* Close all disks and their images. */
|
|
for (d = 0; d < XTA_NUM; d++) {
|
|
drive = &dev->drives[d];
|
|
|
|
if (drive->present)
|
|
hdd_image_close(drive->hdd_num);
|
|
}
|
|
|
|
/* Release the device. */
|
|
free(dev);
|
|
}
|
|
|
|
|
|
const device_t ps1_hdc_device = {
|
|
"PS/1 2011 Fixed Disk Controller",
|
|
DEVICE_ISA | DEVICE_PS2,
|
|
0,
|
|
ps1_hdc_init, ps1_hdc_close, NULL,
|
|
{ NULL }, NULL, NULL,
|
|
NULL
|
|
};
|
|
|
|
|
|
/*
|
|
* Very nasty.
|
|
*
|
|
* The PS/1 systems employ a feedback system where external
|
|
* cards let the system know they were 'addressed' by setting
|
|
* their Card Selected Flag (CSF) in register 0x0091. Driver
|
|
* software can test this register to see if they are talking
|
|
* to hardware or not.
|
|
*
|
|
* This means, that we must somehow do the same, and yes, I
|
|
* agree that the current solution is nasty.
|
|
*/
|
|
void
|
|
ps1_hdc_inform(void *priv, uint8_t *reg_91)
|
|
{
|
|
hdc_t *dev = (hdc_t *)priv;
|
|
|
|
dev->reg_91 = reg_91;
|
|
}
|