182c737921
The SMC FDC37C665 Super I/O chip's IDE handler is now disabled for the Rise Computer R418 (the real board by passes that chip's IDE and uses the SiS 496B IDE controller so this is correct and not a hack), fixes hard disks disappearing on soft reset.
141 lines
4.8 KiB
C
141 lines
4.8 KiB
C
/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include <string.h>
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "i430vx.h"
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static uint8_t card_i430vx[256];
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static void i430vx_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3)
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{
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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void i430vx_write(int func, int addr, uint8_t val, void *priv)
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{
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if (func)
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x59: /*PAM0*/
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if ((card_i430vx[0x59] ^ val) & 0xf0)
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{
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i430vx_map(0xf0000, 0x10000, val >> 4);
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shadowbios = (val & 0x10);
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}
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pclog("i430vx_write : PAM0 write %02X\n", val);
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break;
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case 0x5a: /*PAM1*/
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if ((card_i430vx[0x5a] ^ val) & 0x0f)
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i430vx_map(0xc0000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5a] ^ val) & 0xf0)
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i430vx_map(0xc4000, 0x04000, val >> 4);
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break;
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case 0x5b: /*PAM2*/
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if ((card_i430vx[0x5b] ^ val) & 0x0f)
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i430vx_map(0xc8000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5b] ^ val) & 0xf0)
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i430vx_map(0xcc000, 0x04000, val >> 4);
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break;
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case 0x5c: /*PAM3*/
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if ((card_i430vx[0x5c] ^ val) & 0x0f)
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i430vx_map(0xd0000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5c] ^ val) & 0xf0)
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i430vx_map(0xd4000, 0x04000, val >> 4);
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break;
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case 0x5d: /*PAM4*/
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if ((card_i430vx[0x5d] ^ val) & 0x0f)
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i430vx_map(0xd8000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5d] ^ val) & 0xf0)
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i430vx_map(0xdc000, 0x04000, val >> 4);
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break;
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case 0x5e: /*PAM5*/
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if ((card_i430vx[0x5e] ^ val) & 0x0f)
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i430vx_map(0xe0000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5e] ^ val) & 0xf0)
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i430vx_map(0xe4000, 0x04000, val >> 4);
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pclog("i430vx_write : PAM5 write %02X\n", val);
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break;
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case 0x5f: /*PAM6*/
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if ((card_i430vx[0x5f] ^ val) & 0x0f)
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i430vx_map(0xe8000, 0x04000, val & 0xf);
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if ((card_i430vx[0x5f] ^ val) & 0xf0)
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i430vx_map(0xec000, 0x04000, val >> 4);
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pclog("i430vx_write : PAM6 write %02X\n", val);
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break;
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}
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card_i430vx[addr] = val;
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}
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uint8_t i430vx_read(int func, int addr, void *priv)
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{
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if (func)
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return 0xff;
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return card_i430vx[addr];
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}
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void i430vx_reset(void)
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{
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memset(card_i430vx, 0, 256);
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card_i430vx[0x00] = 0x86; card_i430vx[0x01] = 0x80; /*Intel*/
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card_i430vx[0x02] = 0x30; card_i430vx[0x03] = 0x70; /*82437VX*/
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card_i430vx[0x04] = 0x06; card_i430vx[0x05] = 0x00;
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card_i430vx[0x06] = 0x00; card_i430vx[0x07] = 0x02;
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card_i430vx[0x08] = 0x00; /*A0 stepping*/
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card_i430vx[0x09] = 0x00; card_i430vx[0x0a] = 0x00; card_i430vx[0x0b] = 0x06;
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card_i430vx[0x52] = 0x42; /*256kb PLB cache*/
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card_i430vx[0x53] = 0x14;
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card_i430vx[0x56] = 0x52; /*DRAM control*/
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card_i430vx[0x57] = 0x01;
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card_i430vx[0x60] = card_i430vx[0x61] = card_i430vx[0x62] = card_i430vx[0x63] = card_i430vx[0x64] = 0x02;
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card_i430vx[0x67] = 0x11;
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card_i430vx[0x69] = 0x03;
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card_i430vx[0x70] = 0x20;
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card_i430vx[0x72] = 0x02;
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card_i430vx[0x74] = 0x0e;
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card_i430vx[0x78] = 0x23;
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}
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void i430vx_pci_reset(void)
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{
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i430vx_write(0, 0x59, 0x00, NULL);
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}
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void i430vx_init()
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{
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pci_add_specific(0, i430vx_read, i430vx_write, NULL);
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i430vx_reset();
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pci_reset_handler.pci_master_reset = i430vx_pci_reset;
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}
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