272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C493/82C499 chipset.
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*
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*
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2020 Tiseno100.
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* Copyright 2016-2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/port_92.h>
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#include <86box/plat_unused.h>
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#include <86box/chipset.h>
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typedef struct opti499_t {
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uint8_t idx;
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uint8_t regs[256];
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uint8_t scratch[2];
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} opti499_t;
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/* According to The Last Byte, register 2Dh bit 7 must still be writable, even if it is unused. */
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static uint8_t masks[0x0e] = { 0x3f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xe3, 0xff, 0xfb, 0xff, 0x00, 0xff };
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#ifdef ENABLE_OPTI499_LOG
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int opti499_do_log = ENABLE_OPTI499_LOG;
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static void
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opti499_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti499_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define opti499_log(fmt, ...)
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#endif
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static void
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opti499_recalc(opti499_t *dev)
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{
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uint32_t base;
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uint32_t shflags = 0;
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shadowbios = 0;
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shadowbios_write = 0;
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if (dev->regs[0x22] & 0x80) {
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shadowbios = 1;
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shadowbios_write = 0;
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shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
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} else {
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shadowbios = 0;
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shadowbios_write = 1;
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shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
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}
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mem_set_mem_state_both(0xf0000, 0x10000, shflags);
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for (uint8_t i = 0; i < 8; i++) {
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base = 0xd0000 + (i << 14);
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if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
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shflags = MEM_READ_INTERNAL;
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shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
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} else {
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if (dev->regs[0x2d] & (1 << ((i >> 1) + 2)))
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shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
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else
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shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL;
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}
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mem_set_mem_state_both(base, 0x4000, shflags);
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}
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for (uint8_t i = 0; i < 4; i++) {
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base = 0xc0000 + (i << 14);
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if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
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shflags = MEM_READ_INTERNAL;
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shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
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} else {
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if (dev->regs[0x26] & 0x40) {
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if (dev->regs[0x2d] & (1 << (i >> 1)))
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shflags = MEM_READ_EXTANY;
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else
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shflags = MEM_READ_EXTERNAL;
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shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
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} else {
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if (dev->regs[0x2d] & (1 << (i >> 1)))
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shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
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else
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shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL;
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}
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}
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mem_set_mem_state_both(base, 0x4000, shflags);
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}
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flushmmucache_nopc();
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}
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static void
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opti499_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti499_t *dev = (opti499_t *) priv;
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switch (addr) {
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default:
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break;
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case 0x22:
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opti499_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val);
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dev->idx = val;
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break;
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case 0x24:
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) {
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opti499_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val);
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dev->regs[dev->idx] = val & masks[dev->idx - 0x20];
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if (dev->idx == 0x2a)
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dev->regs[dev->idx] |= 0x04;
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switch (dev->idx) {
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default:
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break;
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case 0x20:
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reset_on_hlt = !(val & 0x02);
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break;
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case 0x21:
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cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10);
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cpu_update_waitstates();
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break;
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case 0x22:
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case 0x23:
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case 0x26:
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case 0x2d:
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opti499_recalc(dev);
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break;
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}
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}
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dev->idx = 0xff;
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break;
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case 0xe1:
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case 0xe2:
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dev->scratch[~addr & 0x01] = val;
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break;
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}
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}
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static uint8_t
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opti499_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti499_t *dev = (opti499_t *) priv;
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switch (addr) {
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default:
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break;
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case 0x22:
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opti499_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret);
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break;
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case 0x24:
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if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) {
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ret = dev->regs[dev->idx];
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opti499_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret);
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}
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dev->idx = 0xff;
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break;
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case 0xe1:
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case 0xe2:
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ret = dev->scratch[~addr & 0x01];
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break;
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}
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return ret;
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}
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static void
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opti499_reset(void *priv)
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{
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opti499_t *dev = (opti499_t *) priv;
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memset(dev->regs, 0xff, sizeof(dev->regs));
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memset(&(dev->regs[0x20]), 0x00, 14 * sizeof(uint8_t));
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dev->scratch[0] = dev->scratch[1] = 0xff;
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dev->regs[0x22] = 0x84;
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dev->regs[0x24] = 0x87;
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dev->regs[0x25] = 0xf0;
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dev->regs[0x27] = 0xd1;
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dev->regs[0x28] = dev->regs[0x2a] = 0x80;
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dev->regs[0x29] = dev->regs[0x2b] = 0x10;
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dev->regs[0x2d] = 0x40;
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reset_on_hlt = 1;
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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opti499_recalc(dev);
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}
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static void
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opti499_close(void *priv)
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{
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opti499_t *dev = (opti499_t *) priv;
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free(dev);
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}
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static void *
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opti499_init(UNUSED(const device_t *info))
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{
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opti499_t *dev = (opti499_t *) calloc(1, sizeof(opti499_t));
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device_add(&port_92_device);
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io_sethandler(0x0022, 0x0001, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
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opti499_reset(dev);
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io_sethandler(0x00e1, 0x0002, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
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return dev;
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}
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const device_t opti499_device = {
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.name = "OPTi 82C499",
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.internal_name = "opti499",
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.flags = 0,
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.local = 1,
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.init = opti499_init,
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.close = opti499_close,
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.reset = opti499_reset,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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