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5f3c976fbe9ab58dfa942ad80ba6e75a579c553d
86Box/src/chipset
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tiseno100 5f3c976fbe Some final touches on the Intel 82335 
Most I could potentially implement are now complete
- Added some commentary
- switched some complex algorithms into definitions for the sake of the code being clean
- Implemented the ROM size determination register just for some Shadow RAM sanity
2020-09-12 15:01:20 +03:00
..
acc2168.c
Revert "Merge branch 'master' of https://github.com/86Box/86Box"
2020-06-07 15:52:45 -03:00
ali1429.c
Mass ALi work
2020-08-10 12:20:29 +03:00
ali1489.c
Some rework on the write procedure of the ALi M1489
2020-08-11 10:36:04 +03:00
ali6117.c
Add non-working AMI M6117 machine
2020-09-08 22:54:30 -03:00
amd640.c
Implemented the AMD 640 chipset
2020-06-22 11:09:11 +03:00
cs4031.c
Chips & Technologies 486 emulation
2020-07-19 13:46:01 +03:00
cs8230.c
Ported the latest cs8230 patch from greatpsycho.
2020-06-17 23:47:37 +02:00
headland.c
Finished the Headland rework, now EMS works on both machines as it should, as does shadowing.
2020-07-14 03:47:37 +02:00
intel_4x0.c
Change special 440BX VPC behavior to is_vpc
2020-07-25 12:28:13 -03:00
intel_420ex.c
Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD
2020-06-26 21:03:46 -03:00
intel_82335.c
Some final touches on the Intel 82335
2020-09-12 15:01:20 +03:00
intel_piix.c
Added a sanity check on write to PIIX4(E) DDMA base PCI registers.
2020-09-08 03:42:42 +02:00
intel_sio.c
Fixed a number of bug sin various modules, VS440FX mostly works now (one bug on soft reset is missing which is left to be debugged).
2020-06-15 17:08:42 +02:00
mcr.c
Moved the two (unused) Intel 386 chipset files to chipset/.
2020-06-13 10:27:07 +02:00
neat.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
opti5x7.c
OPTi 5x7 no longer does excess logging, running of timers on the recompiler is now done on every fourth AT KBC port 61h read instead of every 3F4h read, added some safety precautions to io.c to handle the cases where a handler removes itself, implmented the STPC ELCR and refresh control, and fixed the messed up register reading in the PC87307 and PC87309 implementations.
2020-07-10 02:05:49 +02:00
opti283.c
Commented the OPTi 283 logging code back
2020-07-07 16:40:07 +03:00
opti291.c
Implement F0000-FFFFF shadowing on the OPTi 291
2020-07-08 01:41:18 -06:00
opti495.c
Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur.
2020-07-07 20:43:28 +02:00
opti895.c
Fixed Shadow RAM handling for all OPTi 486 chipsets.
2020-06-30 03:24:06 +02:00
scamp.c
Some SCAMP fixes (of bugs revealed by GCC when compiling 64-bit 86Box).
2020-07-15 05:11:23 +02:00
scat.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c50x.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c310.c
More reorganization and finally merged the two makefiles.
2020-06-13 12:32:09 +02:00
sis_85c471.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00
sis_85c496.c
Fixes to SiS 496/497 and W83787F.
2020-06-29 04:32:30 +02:00
stpc.c
Indentation cleanups on STPC
2020-09-08 21:44:10 -03:00
umc491.c
Added the US Technologies 386 motherboard.
2020-08-19 23:51:40 +03:00
via_apollo.c
Implement DRB locking for VIA Apollo chipsets
2020-06-26 22:05:32 -03:00
via_vpx.c
Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD
2020-06-26 21:03:46 -03:00
via_vt82c49x.c
Minor changes on the VIA 486's.
2020-07-18 14:24:08 +03:00
via_vt82c505.c
VIA 486 bringup
2020-07-17 14:18:54 +03:00
via_vt82c586b.c
A slight reorganization of the source tree and fixed a warning in disk/mo.c.
2020-06-13 10:17:57 +02:00
via_vt82c596b.c
A slight reorganization of the source tree and fixed a warning in disk/mo.c.
2020-06-13 10:17:57 +02:00
vl82c480.c
Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip.
2020-06-30 15:37:07 +02:00
wd76c10.c
Move all include files to src/include
2020-03-29 19:53:29 +02:00