392 lines
14 KiB
C
392 lines
14 KiB
C
#ifdef __amd64__
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#include <stdint.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/mem.h>
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#include "codegen.h"
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#include "codegen_allocator.h"
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#include "codegen_backend.h"
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#include "codegen_backend_x86-64_defs.h"
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#include "codegen_backend_x86-64_ops.h"
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#include "codegen_backend_x86-64_ops_sse.h"
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#include "codegen_reg.h"
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#include "x86.h"
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#if defined(__linux__) || defined(__APPLE__)
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#include <sys/mman.h>
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#include <unistd.h>
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#endif
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#if defined WIN32 || defined _WIN32 || defined _WIN32
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#include <windows.h>
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#endif
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void *codegen_mem_load_byte;
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void *codegen_mem_load_word;
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void *codegen_mem_load_long;
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void *codegen_mem_load_quad;
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void *codegen_mem_load_single;
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void *codegen_mem_load_double;
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void *codegen_mem_store_byte;
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void *codegen_mem_store_word;
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void *codegen_mem_store_long;
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void *codegen_mem_store_quad;
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void *codegen_mem_store_single;
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void *codegen_mem_store_double;
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void *codegen_gpf_rout;
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void *codegen_exit_rout;
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host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] =
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{
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/*Note: while EAX and EDX are normally volatile registers under x86
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calling conventions, the recompiler will explicitly save and restore
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them across funcion calls*/
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{REG_EAX, 0},
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{REG_EBX, 0},
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{REG_EDX, 0}
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};
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host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
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{
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#if WIN64
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/*Windows x86-64 calling convention preserves XMM6-XMM15*/
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{REG_XMM6, 0},
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{REG_XMM7, 0},
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#else
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/*System V AMD64 calling convention does not preserve any XMM registers*/
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{REG_XMM6, HOST_REG_FLAG_VOLATILE},
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{REG_XMM7, HOST_REG_FLAG_VOLATILE},
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#endif
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{REG_XMM1, HOST_REG_FLAG_VOLATILE},
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{REG_XMM2, HOST_REG_FLAG_VOLATILE},
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{REG_XMM3, HOST_REG_FLAG_VOLATILE},
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{REG_XMM4, HOST_REG_FLAG_VOLATILE},
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{REG_XMM5, HOST_REG_FLAG_VOLATILE}
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};
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static void build_load_routine(codeblock_t *block, int size, int is_float)
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{
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uint8_t *branch_offset;
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uint8_t *misaligned_offset;
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/*In - ESI = address
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Out - ECX = data, ESI = abrt*/
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/*MOV ECX, ESI
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SHR ESI, 12
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MOV RSI, [readlookup2+ESI*4]
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CMP ESI, -1
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JNZ +
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MOVZX ECX, B[RSI+RCX]
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XOR ESI,ESI
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RET
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* PUSH EAX
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PUSH EDX
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PUSH ECX
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CALL readmembl
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POP ECX
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POP EDX
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POP EAX
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MOVZX ECX, AL
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RET
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*/
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host_x86_MOV32_REG_REG(block, REG_ECX, REG_ESI);
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host_x86_SHR32_IMM(block, REG_ESI, 12);
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host_x86_MOV64_REG_IMM(block, REG_RDI, (uint64_t)(uintptr_t)readlookup2);
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host_x86_MOV64_REG_BASE_INDEX_SHIFT(block, REG_RSI, REG_RDI, REG_RSI, 3);
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if (size != 1)
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{
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host_x86_TEST32_REG_IMM(block, REG_ECX, size-1);
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misaligned_offset = host_x86_JNZ_short(block);
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}
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host_x86_CMP64_REG_IMM(block, REG_RSI, (uint32_t)-1);
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branch_offset = host_x86_JZ_short(block);
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if (size == 1 && !is_float)
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host_x86_MOVZX_BASE_INDEX_32_8(block, REG_ECX, REG_RSI, REG_RCX);
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else if (size == 2 && !is_float)
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host_x86_MOVZX_BASE_INDEX_32_16(block, REG_ECX, REG_RSI, REG_RCX);
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else if (size == 4 && !is_float)
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host_x86_MOV32_REG_BASE_INDEX(block, REG_ECX, REG_RSI, REG_RCX);
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else if (size == 4 && is_float)
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host_x86_CVTSS2SD_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_RSI, REG_RCX);
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else if (size == 8)
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host_x86_MOVQ_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_RSI, REG_RCX);
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else
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fatal("build_load_routine: size=%i\n", size);
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host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
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host_x86_RET(block);
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*branch_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 1;
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if (size != 1)
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*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
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host_x86_PUSH(block, REG_RAX);
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host_x86_PUSH(block, REG_RDX);
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#if WIN64
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host_x86_SUB64_REG_IMM(block, REG_RSP, 0x20);
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//host_x86_MOV32_REG_REG(block, REG_ECX, uop->imm_data);
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#else
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host_x86_MOV32_REG_REG(block, REG_EDI, REG_ECX);
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#endif
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if (size == 1 && !is_float)
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{
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host_x86_CALL(block, (void *)readmembl);
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host_x86_MOVZX_REG_32_8(block, REG_ECX, REG_EAX);
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}
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else if (size == 2 && !is_float)
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{
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host_x86_CALL(block, (void *)readmemwl);
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host_x86_MOVZX_REG_32_16(block, REG_ECX, REG_EAX);
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}
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else if (size == 4 && !is_float)
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{
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host_x86_CALL(block, (void *)readmemll);
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host_x86_MOV32_REG_REG(block, REG_ECX, REG_EAX);
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}
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else if (size == 4 && is_float)
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{
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host_x86_CALL(block, (void *)readmemll);
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host_x86_MOVD_XREG_REG(block, REG_XMM_TEMP, REG_EAX);
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host_x86_CVTSS2SD_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP);
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}
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else if (size == 8)
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{
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host_x86_CALL(block, (void *)readmemql);
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host_x86_MOVQ_XREG_REG(block, REG_XMM_TEMP, REG_RAX);
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}
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#if WIN64
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host_x86_ADD64_REG_IMM(block, REG_RSP, 0x20);
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#endif
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host_x86_POP(block, REG_RDX);
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host_x86_POP(block, REG_RAX);
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host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
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host_x86_RET(block);
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}
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static void build_store_routine(codeblock_t *block, int size, int is_float)
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{
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uint8_t *branch_offset;
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uint8_t *misaligned_offset;
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/*In - ECX = data, ESI = address
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Out - ESI = abrt
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Corrupts EDI*/
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/*MOV EDI, ESI
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SHR ESI, 12
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MOV ESI, [writelookup2+ESI*4]
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CMP ESI, -1
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JNZ +
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MOV [RSI+RDI], ECX
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XOR ESI,ESI
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RET
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* PUSH EAX
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PUSH EDX
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PUSH ECX
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CALL writemembl
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POP ECX
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POP EDX
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POP EAX
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MOVZX ECX, AL
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RET
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*/
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host_x86_MOV32_REG_REG(block, REG_EDI, REG_ESI);
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host_x86_SHR32_IMM(block, REG_ESI, 12);
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host_x86_MOV64_REG_IMM(block, REG_R8, (uint64_t)(uintptr_t)writelookup2);
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host_x86_MOV64_REG_BASE_INDEX_SHIFT(block, REG_RSI, REG_R8, REG_RSI, 3);
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if (size != 1)
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{
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host_x86_TEST32_REG_IMM(block, REG_EDI, size-1);
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misaligned_offset = host_x86_JNZ_short(block);
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}
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host_x86_CMP64_REG_IMM(block, REG_RSI, (uint32_t)-1);
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branch_offset = host_x86_JZ_short(block);
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if (size == 1 && !is_float)
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host_x86_MOV8_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
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else if (size == 2 && !is_float)
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host_x86_MOV16_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
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else if (size == 4 && !is_float)
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host_x86_MOV32_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
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else if (size == 4 && is_float)
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host_x86_MOVD_BASE_INDEX_XREG(block, REG_RSI, REG_RDI, REG_XMM_TEMP);
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else if (size == 8)
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host_x86_MOVQ_BASE_INDEX_XREG(block, REG_RSI, REG_RDI, REG_XMM_TEMP);
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else
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fatal("build_store_routine: size=%i\n", size);
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host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
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host_x86_RET(block);
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*branch_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)branch_offset) - 1;
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if (size != 1)
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*misaligned_offset = (uint8_t)((uintptr_t)&block_write_data[block_pos] - (uintptr_t)misaligned_offset) - 1;
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host_x86_PUSH(block, REG_RAX);
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host_x86_PUSH(block, REG_RDX);
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#if WIN64
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host_x86_SUB64_REG_IMM(block, REG_RSP, 0x28);
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if (size == 4 && is_float)
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host_x86_MOVD_REG_XREG(block, REG_EDX, REG_XMM_TEMP); //data
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else if (size == 8)
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host_x86_MOVQ_REG_XREG(block, REG_RDX, REG_XMM_TEMP); //data
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else
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host_x86_MOV32_REG_REG(block, REG_EDX, REG_ECX); //data
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host_x86_MOV32_REG_REG(block, REG_ECX, REG_EDI); //address
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#else
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host_x86_SUB64_REG_IMM(block, REG_RSP, 0x8);
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//host_x86_MOV32_REG_REG(block, REG_EDI, REG_ECX); //address
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if (size == 4 && is_float)
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host_x86_MOVD_REG_XREG(block, REG_ESI, REG_XMM_TEMP); //data
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else if (size == 8)
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host_x86_MOVQ_REG_XREG(block, REG_RSI, REG_XMM_TEMP); //data
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else
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host_x86_MOV32_REG_REG(block, REG_ESI, REG_ECX); //data
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#endif
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if (size == 1)
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host_x86_CALL(block, (void *)writemembl);
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else if (size == 2)
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host_x86_CALL(block, (void *)writememwl);
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else if (size == 4)
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host_x86_CALL(block, (void *)writememll);
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else if (size == 8)
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host_x86_CALL(block, (void *)writememql);
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#if WIN64
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host_x86_ADD64_REG_IMM(block, REG_RSP, 0x28);
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#else
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host_x86_ADD64_REG_IMM(block, REG_RSP, 0x8);
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#endif
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host_x86_POP(block, REG_RDX);
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host_x86_POP(block, REG_RAX);
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host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
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host_x86_RET(block);
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}
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static void build_loadstore_routines(codeblock_t *block)
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{
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codegen_mem_load_byte = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 1, 0);
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codegen_mem_load_word = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 2, 0);
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codegen_mem_load_long = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 4, 0);
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codegen_mem_load_quad = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 8, 0);
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codegen_mem_load_single = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 4, 1);
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codegen_mem_load_double = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 8, 1);
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codegen_mem_store_byte = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 1, 0);
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codegen_mem_store_word = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 2, 0);
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codegen_mem_store_long = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 4, 0);
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codegen_mem_store_quad = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 8, 0);
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codegen_mem_store_single = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 4, 1);
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codegen_mem_store_double = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 8, 1);
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}
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void codegen_backend_init()
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{
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codeblock_t *block;
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int c;
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#if defined(__linux__) || defined(__APPLE__)
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void *start;
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size_t len;
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long pagesize = sysconf(_SC_PAGESIZE);
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long pagemask = ~(pagesize - 1);
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#endif
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codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
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codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
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memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
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memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
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for (c = 0; c < BLOCK_SIZE; c++)
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codeblock[c].pc = BLOCK_PC_INVALID;
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block_current = 0;
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block_pos = 0;
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block = &codeblock[block_current];
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codeblock[block_current].head_mem_block = codegen_allocator_allocate(NULL, block_current);
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codeblock[block_current].data = codeblock_allocator_get_ptr(codeblock[block_current].head_mem_block);
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block_write_data = codeblock[block_current].data;
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build_loadstore_routines(&codeblock[block_current]);
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codegen_gpf_rout = &codeblock[block_current].data[block_pos];
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#if WIN64
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host_x86_XOR32_REG_REG(block, REG_ECX, REG_ECX);
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host_x86_XOR32_REG_REG(block, REG_EDX, REG_EDX);
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#else
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host_x86_XOR32_REG_REG(block, REG_EDI, REG_EDI);
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host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
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#endif
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/* host_x86_CALL(block, (uintptr_t)x86gpf); */
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host_x86_CALL(block, (void *)x86gpf);
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codegen_exit_rout = &codeblock[block_current].data[block_pos];
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host_x86_ADD64_REG_IMM(block, REG_RSP, 0x38);
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host_x86_POP(block, REG_R15);
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host_x86_POP(block, REG_R14);
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host_x86_POP(block, REG_R13);
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host_x86_POP(block, REG_R12);
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host_x86_POP(block, REG_RDI);
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host_x86_POP(block, REG_RSI);
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host_x86_POP(block, REG_RBP);
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host_x86_POP(block, REG_RDX);
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host_x86_RET(block);
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block_write_data = NULL;
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asm(
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"stmxcsr %0\n"
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: "=m" (cpu_state.old_fp_control)
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);
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cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
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}
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void codegen_set_rounding_mode(int mode)
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{
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cpu_state.new_fp_control = (cpu_state.old_fp_control & ~0x6000) | (mode << 13);
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}
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void codegen_backend_prologue(codeblock_t *block)
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{
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block_pos = BLOCK_START; /*Entry code*/
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host_x86_PUSH(block, REG_RBX);
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host_x86_PUSH(block, REG_RBP);
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host_x86_PUSH(block, REG_RSI);
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host_x86_PUSH(block, REG_RDI);
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host_x86_PUSH(block, REG_R12);
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host_x86_PUSH(block, REG_R13);
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host_x86_PUSH(block, REG_R14);
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host_x86_PUSH(block, REG_R15);
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host_x86_SUB64_REG_IMM(block, REG_RSP, 0x38);
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host_x86_MOV64_REG_IMM(block, REG_RBP, ((uintptr_t)&cpu_state) + 128);
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if (block->flags & CODEBLOCK_HAS_FPU)
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{
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host_x86_MOV32_REG_ABS(block, REG_EAX, &cpu_state.TOP);
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host_x86_SUB32_REG_IMM(block, REG_EAX, block->TOP);
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host_x86_MOV32_BASE_OFFSET_REG(block, REG_RSP, IREG_TOP_diff_stack_offset, REG_EAX);
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}
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if (block->flags & CODEBLOCK_NO_IMMEDIATES)
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host_x86_MOV64_REG_IMM(block, REG_R12, (uintptr_t)ram);
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}
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void codegen_backend_epilogue(codeblock_t *block)
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{
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host_x86_ADD64_REG_IMM(block, REG_RSP, 0x38);
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host_x86_POP(block, REG_R15);
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host_x86_POP(block, REG_R14);
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host_x86_POP(block, REG_R13);
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host_x86_POP(block, REG_R12);
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host_x86_POP(block, REG_RDI);
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host_x86_POP(block, REG_RSI);
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host_x86_POP(block, REG_RBP);
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host_x86_POP(block, REG_RDX);
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host_x86_RET(block);
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}
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#endif
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