712 lines
23 KiB
C
712 lines
23 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Universal Serial Bus emulation (currently dummy UHCI and
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* OHCI).
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/timer.h>
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#include <86box/usb.h>
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#include <86box/dma.h>
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#ifdef ENABLE_USB_LOG
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int usb_do_log = ENABLE_USB_LOG;
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static void
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usb_log(const char *fmt, ...)
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{
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va_list ap;
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if (usb_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define usb_log(fmt, ...)
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#endif
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/* OHCI registers */
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enum
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{
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OHCI_HcRevision = 0x00 /* 0x00 */,
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OHCI_HcControl = 0x01 /* 0x04 */,
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OHCI_HcCommandStatus = 0x02 /* 0x08 */,
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OHCI_HcInterruptStatus = 0x03 /* 0x0c */,
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OHCI_HcInterruptEnable = 0x04 /* 0x10 */,
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OHCI_HcInterruptDisable = 0x05 /* 0x14 */,
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OHCI_HcHCCA = 0x06 /* 0x18 */,
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OHCI_HcPeriodCurrentED = 0x07 /* 0x1c */,
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OHCI_HcControlHeadED = 0x08 /* 0x20 */,
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OHCI_HcControlCurrentED = 0x09 /* 0x24 */,
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OHCI_HcBulkHeadED = 0x0a /* 0x28 */,
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OHCI_HcBulkCurrentED = 0x0b /* 0x2c */,
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OHCI_HcDoneHead = 0x0c /* 0x30 */,
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OHCI_HcFmInterval = 0x0d /* 0x34 */,
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OHCI_HcFmRemaining = 0x0e /* 0x38 */,
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OHCI_HcFmNumber = 0x0f /* 0x3c */,
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OHCI_HcPeriodicStart = 0x10 /* 0x40 */,
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OHCI_HcLSThreshold = 0x11 /* 0x44 */,
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OHCI_HcRhDescriptorA = 0x12 /* 0x48 */,
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OHCI_HcRhDescriptorB = 0x13 /* 0x4c */,
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OHCI_HcRhStatus = 0x14 /* 0x50 */,
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OHCI_HcRhPortStatus1 = 0x15 /* 0x54 */,
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OHCI_HcRhPortStatus2 = 0x16 /* 0x58 */,
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OHCI_HcRhPortStatus3 = 0x17 /* 0x5c */
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};
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enum
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{
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OHCI_aHcRevision = 0x00,
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OHCI_aHcControl = 0x04,
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OHCI_aHcCommandStatus = 0x08,
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OHCI_aHcInterruptStatus = 0x0c,
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OHCI_aHcInterruptEnable = 0x10,
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OHCI_aHcInterruptDisable = 0x14,
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OHCI_aHcHCCA = 0x18,
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OHCI_aHcPeriodCurrentED = 0x1c,
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OHCI_aHcControlHeadED = 0x20,
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OHCI_aHcControlCurrentED = 0x24,
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OHCI_aHcBulkHeadED = 0x28,
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OHCI_aHcBulkCurrentED = 0x2c,
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OHCI_aHcDoneHead = 0x30,
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OHCI_aHcFmInterval = 0x34,
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OHCI_aHcFmRemaining = 0x38,
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OHCI_aHcFmNumber = 0x3c,
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OHCI_aHcPeriodicStart = 0x40,
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OHCI_aHcLSThreshold = 0x44,
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OHCI_aHcRhDescriptorA = 0x48,
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OHCI_aHcRhDescriptorB = 0x4c,
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OHCI_aHcRhStatus = 0x50,
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OHCI_aHcRhPortStatus1 = 0x54,
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OHCI_aHcRhPortStatus2 = 0x58,
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OHCI_aHcRhPortStatus3 = 0x5c
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};
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/* OHCI HcInterruptEnable/Disable bits */
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enum
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{
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OHCI_HcInterruptEnable_SO = 1 << 0,
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OHCI_HcInterruptEnable_WDH = 1 << 1,
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OHCI_HcInterruptEnable_SF = 1 << 2,
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OHCI_HcInterruptEnable_RD = 1 << 3,
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OHCI_HcInterruptEnable_UE = 1 << 4,
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OHCI_HcInterruptEnable_HNO = 1 << 5,
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OHCI_HcInterruptEnable_RHSC = 1 << 6,
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};
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static void
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usb_interrupt_ohci(usb_t *dev, uint32_t level)
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{
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if (dev->ohci_mmio[OHCI_HcControl].b[1] & 1) {
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if (dev->usb_params && dev->usb_params->smi_handle && !dev->usb_params->smi_handle(dev, dev->usb_params->parent_priv))
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return;
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if (level)
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smi_raise();
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} else if (dev->usb_params != NULL) {
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if ((dev->usb_params->parent_priv != NULL) && (dev->usb_params->update_interrupt != NULL))
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dev->usb_params->update_interrupt(dev, dev->usb_params->parent_priv);
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}
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}
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static uint8_t
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uhci_reg_read(uint16_t addr, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t ret, *regs = dev->uhci_io;
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addr &= 0x0000001f;
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ret = regs[addr];
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return ret;
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}
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static void
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uhci_reg_write(uint16_t addr, uint8_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t *regs = dev->uhci_io;
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addr &= 0x0000001f;
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switch (addr) {
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case 0x02:
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regs[0x02] &= ~(val & 0x3f);
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break;
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case 0x04:
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regs[0x04] = (val & 0x0f);
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break;
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case 0x09:
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regs[0x09] = (val & 0xf0);
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break;
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case 0x0a:
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case 0x0b:
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regs[addr] = val;
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break;
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case 0x0c:
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regs[0x0c] = (val & 0x7f);
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break;
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}
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}
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static void
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uhci_reg_writew(uint16_t addr, uint16_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint16_t *regs = (uint16_t *) dev->uhci_io;
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addr &= 0x0000001f;
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switch (addr) {
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case 0x00:
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if ((val & 0x0001) && !(regs[0x00] & 0x0001))
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regs[0x01] &= ~0x20;
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else if (!(val & 0x0001))
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regs[0x01] |= 0x20;
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regs[0x00] = (val & 0x00ff);
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break;
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case 0x06:
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regs[0x03] = (val & 0x07ff);
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break;
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case 0x10:
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case 0x12:
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regs[addr >> 1] = ((regs[addr >> 1] & 0xedbb) | (val & 0x1244)) & ~(val & 0x080a);
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break;
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default:
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uhci_reg_write(addr, val & 0xff, p);
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uhci_reg_write(addr + 1, (val >> 8) & 0xff, p);
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break;
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}
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}
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void
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uhci_update_io_mapping(usb_t *dev, uint8_t base_l, uint8_t base_h, int enable)
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{
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if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
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io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
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dev->uhci_io_base = base_l | (base_h << 8);
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dev->uhci_enable = enable;
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if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
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io_sethandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
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}
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static uint8_t
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ohci_mmio_read(uint32_t addr, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t ret = 0x00;
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#ifdef ENABLE_USB_LOG
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uint32_t old_addr = addr;
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#endif
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addr &= 0x00000fff;
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ret = dev->ohci_mmio[addr >> 2].b[addr & 3];
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switch (addr) {
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case 0x101:
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ret = (ret & 0xfe) | (!!mem_a20_key);
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break;
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case OHCI_aHcRhPortStatus1 + 1:
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case OHCI_aHcRhPortStatus2 + 1:
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case OHCI_aHcRhPortStatus3 + 1:
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ret |= 0x1;
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break;
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case OHCI_aHcInterruptDisable:
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case OHCI_aHcInterruptDisable + 1:
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case OHCI_aHcInterruptDisable + 2:
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case OHCI_aHcInterruptDisable + 3:
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ret = dev->ohci_mmio[OHCI_HcInterruptEnable].b[addr & 3];
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default:
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break;
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}
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if (addr == 0x101)
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ret = (ret & 0xfe) | (!!mem_a20_key);
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#ifdef ENABLE_USB_LOG
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usb_log("[R] %08X = %04X\n", old_addr, ret);
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#endif
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return ret;
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}
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static uint16_t
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ohci_mmio_readw(uint32_t addr, void *p)
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{
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return ohci_mmio_read(addr, p) | (ohci_mmio_read(addr + 1, p) << 8);
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}
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static uint32_t
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ohci_mmio_readl(uint32_t addr, void *p)
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{
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return ohci_mmio_readw(addr, p) | (ohci_mmio_readw(addr + 2, p) << 16);
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}
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static void
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ohci_update_irq(usb_t *dev)
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{
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uint32_t level = !!(dev->ohci_mmio[OHCI_HcInterruptStatus].l & dev->ohci_mmio[OHCI_HcInterruptEnable].l);
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if (level != dev->irq_level) {
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dev->irq_level = level;
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usb_interrupt_ohci(dev, level);
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}
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}
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void
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ohci_set_interrupt(usb_t *dev, uint8_t bit)
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{
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if (!(dev->ohci_mmio[OHCI_HcInterruptEnable].b[3] & 0x80))
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return;
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if (!(dev->ohci_mmio[OHCI_HcInterruptEnable].b[0] & bit))
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return;
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if (dev->ohci_mmio[OHCI_HcInterruptDisable].b[0] & bit)
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return;
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dev->ohci_mmio[OHCI_HcInterruptStatus].b[0] |= bit;
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ohci_update_irq(dev);
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}
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void
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ohci_end_of_frame(usb_t* dev)
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{
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/* TODO: Put endpoint and transfer descriptor processing here. */
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dev->ohci_mmio[OHCI_HcFmNumber].w[0]++;
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}
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void
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ohci_start_of_frame(usb_t* dev)
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{
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ohci_set_interrupt(dev, OHCI_HcInterruptEnable_SO);
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}
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void
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ohci_update_frame_counter(void* priv)
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{
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usb_t *dev = (usb_t *) priv;
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dev->ohci_mmio[OHCI_HcFmRemaining].w[0] &= 0x3fff;
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if (dev->ohci_mmio[OHCI_HcFmRemaining].w[0] == 0) {
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ohci_end_of_frame(dev);
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dev->ohci_mmio[OHCI_HcFmRemaining].w[0] = dev->ohci_mmio[OHCI_HcFmInterval].w[0] & 0x3fff;
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dev->ohci_mmio[OHCI_HcFmRemaining].l &= ~(1 << 31);
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dev->ohci_mmio[OHCI_HcFmRemaining].l |= dev->ohci_mmio[OHCI_HcFmInterval].l & (1 << 31);
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ohci_start_of_frame(dev);
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timer_on_auto(&dev->ohci_frame_timer, 1. / (12. * 1000. * 1000.));
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return;
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}
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if (dev->ohci_mmio[OHCI_HcFmRemaining].w[0]) dev->ohci_mmio[OHCI_HcFmRemaining].w[0]--;
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timer_on_auto(&dev->ohci_frame_timer, 1. / (12. * 1000. * 1000.));
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}
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void
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ohci_poll_interrupt_descriptors(void* priv)
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{
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usb_t *dev = (usb_t *) priv;
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/* TODO: Actually poll the interrupt descriptors. */
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dev->ohci_interrupt_counter++;
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timer_on_auto(&dev->ohci_interrupt_desc_poll_timer, 1000.);
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}
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void
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ohci_port_reset_callback(void* priv)
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{
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usb_t *dev = (usb_t *) priv;
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dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] &= ~0x10;
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dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] |= 0x10;
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}
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void
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ohci_port_reset_callback_2(void* priv)
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{
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usb_t *dev = (usb_t *) priv;
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dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] &= ~0x10;
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dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] |= 0x10;
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}
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static void
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ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t old;
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#ifdef ENABLE_USB_LOG
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usb_log("[W] %08X = %04X\n", addr, val);
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#endif
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addr &= 0x00000fff;
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switch (addr) {
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case OHCI_aHcControl:
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if ((val & 0xc0) == 0x00) {
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/* UsbReset */
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dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] = dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] = 0x16;
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}
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break;
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case OHCI_aHcCommandStatus:
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/* bit OwnershipChangeRequest triggers an ownership change (SMM <-> OS) */
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if (val & 0x08) {
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dev->ohci_mmio[OHCI_HcInterruptStatus].b[3] = 0x40;
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if ((dev->ohci_mmio[OHCI_HcInterruptEnable].b[3] & 0xc0) == 0xc0)
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smi_raise();
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}
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/* bit HostControllerReset must be cleared for the controller to be seen as initialized */
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if (val & 0x01) {
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memset(dev->ohci_mmio, 0x00, sizeof(dev->ohci_mmio));
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dev->ohci_mmio[OHCI_HcRevision].b[0] = 0x10;
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dev->ohci_mmio[OHCI_HcRevision].b[1] = 0x01;
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dev->ohci_mmio[OHCI_HcRhDescriptorA].b[0] = 0x02;
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val &= ~0x01;
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}
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break;
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case OHCI_aHcHCCA:
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return;
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case OHCI_aHcInterruptEnable:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x7f);
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dev->ohci_mmio[OHCI_HcInterruptDisable].b[0] &= ~(val & 0x7f);
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ohci_update_irq(dev);
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return;
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case OHCI_aHcInterruptEnable + 1:
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case OHCI_aHcInterruptEnable + 2:
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return;
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case OHCI_aHcInterruptEnable + 3:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0xc0);
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dev->ohci_mmio[OHCI_HcInterruptDisable].b[3] &= ~(val & 0xc0);
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ohci_update_irq(dev);
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return;
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case OHCI_aHcInterruptDisable:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x7f);
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dev->ohci_mmio[OHCI_HcInterruptEnable].b[0] &= ~(val & 0x7f);
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ohci_update_irq(dev);
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return;
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case OHCI_aHcInterruptDisable + 1:
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case OHCI_aHcInterruptDisable + 2:
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return;
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case OHCI_aHcInterruptDisable + 3:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0xc0);
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dev->ohci_mmio[OHCI_HcInterruptEnable].b[3] &= ~(val & 0xc0);
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ohci_update_irq(dev);
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return;
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case OHCI_aHcInterruptStatus:
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dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~(val & 0x7f);
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return;
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case OHCI_aHcInterruptStatus + 1:
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case OHCI_aHcInterruptStatus + 2:
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return;
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case OHCI_aHcInterruptStatus + 3:
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dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~(val & 0x40);
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return;
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case OHCI_aHcFmRemaining + 3:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x80);
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return;
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case OHCI_aHcFmRemaining + 1:
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case OHCI_aHcPeriodicStart + 1:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x3f);
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return;
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case OHCI_aHcLSThreshold + 1:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x0f);
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return;
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case OHCI_aHcFmRemaining + 2:
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case OHCI_aHcFmNumber + 2:
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case OHCI_aHcFmNumber + 3:
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case OHCI_aHcPeriodicStart + 2:
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case OHCI_aHcPeriodicStart + 3:
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case OHCI_aHcLSThreshold + 2:
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case OHCI_aHcLSThreshold + 3:
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case OHCI_aHcRhDescriptorA:
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case OHCI_aHcRhDescriptorA + 2:
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return;
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case OHCI_aHcRhDescriptorA + 1:
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dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x1b);
|
|
if (val & 0x02) {
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[1] |= 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[1] |= 0x01;
|
|
}
|
|
return;
|
|
case OHCI_aHcRhDescriptorA + 3:
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x03);
|
|
return;
|
|
case OHCI_aHcRhDescriptorB:
|
|
case OHCI_aHcRhDescriptorB + 2:
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0x06);
|
|
if ((addr == OHCI_HcRhDescriptorB) && !(val & 0x04)) {
|
|
if (!(dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] & 0x01))
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] |= 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] |= 0x01;
|
|
}
|
|
if ((addr == OHCI_HcRhDescriptorB) && !(val & 0x02)) {
|
|
if (!(dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] & 0x01))
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] |= 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] |= 0x01;
|
|
}
|
|
return;
|
|
case OHCI_aHcRhDescriptorB + 1:
|
|
case OHCI_aHcRhDescriptorB + 3:
|
|
return;
|
|
case OHCI_aHcRhStatus:
|
|
if (val & 0x01) {
|
|
if ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) {
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[1] &= ~0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[1] &= ~0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] &= ~0x17;
|
|
} else if ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x01) {
|
|
if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x02)) {
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[1] &= ~0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] &= ~0x17;
|
|
}
|
|
if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x04)) {
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[1] &= ~0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] &= ~0x17;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
case OHCI_aHcRhStatus + 1:
|
|
if (val & 0x80)
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x80;
|
|
return;
|
|
case OHCI_aHcRhStatus + 2:
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~(val & 0x02);
|
|
if (val & 0x01) {
|
|
if ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) {
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[1] |= 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[1] |= 0x01;
|
|
} else if ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x01) {
|
|
if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x02))
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[1] |= 0x01;
|
|
if (!(dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x04))
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[1] |= 0x01;
|
|
}
|
|
}
|
|
return;
|
|
case OHCI_aHcRhStatus + 3:
|
|
if (val & 0x80)
|
|
dev->ohci_mmio[OHCI_HcRhStatus].b[1] &= ~0x80;
|
|
return;
|
|
case OHCI_aHcRhPortStatus1:
|
|
case OHCI_aHcRhPortStatus2:
|
|
old = dev->ohci_mmio[addr >> 2].b[addr & 3];
|
|
|
|
if (val & 0x10) {
|
|
if (old & 0x01) {
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x10;
|
|
timer_on_auto(&dev->ohci_port_reset_timer[(addr - OHCI_aHcRhPortStatus1) / 4], 10000.);
|
|
} else
|
|
dev->ohci_mmio[(addr + 2) >> 2].b[(addr + 2) & 3] |= 0x01;
|
|
}
|
|
if (val & 0x08)
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~0x04;
|
|
if (val & 0x04)
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x04;
|
|
if (val & 0x02) {
|
|
if (old & 0x01)
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x02;
|
|
else
|
|
dev->ohci_mmio[(addr + 2) >> 2].b[(addr + 2) & 3] |= 0x01;
|
|
}
|
|
if (val & 0x01) {
|
|
if (old & 0x01)
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~0x02;
|
|
else
|
|
dev->ohci_mmio[(addr + 2) >> 2].b[(addr + 2) & 3] |= 0x01;
|
|
}
|
|
|
|
if (!(dev->ohci_mmio[addr >> 2].b[addr & 3] & 0x04) && (old & 0x04))
|
|
dev->ohci_mmio[(addr + 2) >> 2].b[(addr + 2) & 3] |= 0x04;
|
|
/* if (!(dev->ohci_mmio[addr >> 2].b[addr & 3] & 0x02))
|
|
dev->ohci_mmio[(addr + 2) >> 2].b[(addr + 2) & 3] |= 0x02; */
|
|
return;
|
|
case OHCI_aHcRhPortStatus1 + 1:
|
|
if ((val & 0x02) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x02)) {
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus1].b[2] &= ~0x17;
|
|
}
|
|
if ((val & 0x01) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x02)) {
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[0] &= ~0x17;
|
|
dev->ohci_mmio[OHCI_HcRhPortStatus2].b[2] &= ~0x17;
|
|
}
|
|
return;
|
|
case OHCI_aHcRhPortStatus2 + 1:
|
|
if ((val & 0x02) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x04))
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~0x01;
|
|
if ((val & 0x01) && ((dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] & 0x03) == 0x00) && (dev->ohci_mmio[OHCI_HcRhDescriptorB].b[2] & 0x04))
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] |= 0x01;
|
|
return;
|
|
case OHCI_aHcRhPortStatus1 + 2:
|
|
case OHCI_aHcRhPortStatus2 + 2:
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] &= ~(val & 0x1f);
|
|
return;
|
|
case OHCI_aHcRhPortStatus1 + 3:
|
|
case OHCI_aHcRhPortStatus2 + 3:
|
|
return;
|
|
case OHCI_aHcDoneHead:
|
|
case OHCI_aHcBulkCurrentED:
|
|
case OHCI_aHcBulkHeadED:
|
|
case OHCI_aHcControlCurrentED:
|
|
case OHCI_aHcControlHeadED:
|
|
case OHCI_aHcPeriodCurrentED:
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] = (val & 0xf0);
|
|
return;
|
|
}
|
|
|
|
dev->ohci_mmio[addr >> 2].b[addr & 3] = val;
|
|
}
|
|
|
|
static void
|
|
ohci_mmio_writew(uint32_t addr, uint16_t val, void *p)
|
|
{
|
|
ohci_mmio_write(addr, val & 0xff, p);
|
|
ohci_mmio_write(addr + 1, val >> 8, p);
|
|
}
|
|
|
|
static void
|
|
ohci_mmio_writel(uint32_t addr, uint32_t val, void *p)
|
|
{
|
|
ohci_mmio_writew(addr, val & 0xffff, p);
|
|
ohci_mmio_writew(addr + 2, val >> 16, p);
|
|
}
|
|
|
|
void
|
|
ohci_update_mem_mapping(usb_t *dev, uint8_t base1, uint8_t base2, uint8_t base3, int enable)
|
|
{
|
|
if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
|
|
mem_mapping_disable(&dev->ohci_mmio_mapping);
|
|
|
|
dev->ohci_mem_base = ((base1 << 8) | (base2 << 16) | (base3 << 24)) & 0xfffff000;
|
|
dev->ohci_enable = enable;
|
|
|
|
if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
|
|
mem_mapping_set_addr(&dev->ohci_mmio_mapping, dev->ohci_mem_base, 0x1000);
|
|
|
|
usb_log("ohci_update_mem_mapping(): OHCI %sabled at %08X\n", dev->ohci_enable ? "en" : "dis", dev->ohci_mem_base);
|
|
}
|
|
|
|
uint8_t
|
|
usb_attach_device(usb_t *dev, usb_device_t* device, uint8_t bus_type)
|
|
{
|
|
return 255;
|
|
}
|
|
|
|
void
|
|
usb_detach_device(usb_t *dev, uint8_t port, uint8_t bus_type)
|
|
{
|
|
/* Unused. */
|
|
}
|
|
|
|
static void
|
|
usb_reset(void *priv)
|
|
{
|
|
usb_t *dev = (usb_t *) priv;
|
|
|
|
memset(dev->uhci_io, 0x00, sizeof(dev->uhci_io));
|
|
dev->uhci_io[0x0c] = 0x40;
|
|
dev->uhci_io[0x10] = dev->uhci_io[0x12] = 0x80;
|
|
|
|
memset(dev->ohci_mmio, 0x00, sizeof(dev->ohci_mmio));
|
|
dev->ohci_mmio[OHCI_HcRevision].b[0] = 0x10;
|
|
dev->ohci_mmio[OHCI_HcRevision].b[1] = 0x01;
|
|
dev->ohci_mmio[OHCI_HcRhDescriptorA].b[0] = 0x02;
|
|
dev->ohci_mmio[OHCI_HcRhDescriptorA].b[1] = 0x02;
|
|
|
|
io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
|
|
dev->uhci_enable = 0;
|
|
|
|
mem_mapping_disable(&dev->ohci_mmio_mapping);
|
|
dev->ohci_enable = 0;
|
|
|
|
usb_log("usb_reset(): OHCI %sabled at %08X\n", dev->ohci_enable ? "en" : "dis", dev->ohci_mem_base);
|
|
usb_log("usb_reset(): map = %08X\n", &dev->ohci_mmio_mapping);
|
|
}
|
|
|
|
static void
|
|
usb_close(void *priv)
|
|
{
|
|
usb_t *dev = (usb_t *) priv;
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
usb_init_ext(const device_t *info, void *params)
|
|
{
|
|
usb_t *dev;
|
|
|
|
dev = (usb_t *) calloc(1, sizeof(usb_t));
|
|
if (dev == NULL)
|
|
return (NULL);
|
|
|
|
dev->usb_params = (usb_params_t *) params;
|
|
|
|
mem_mapping_add(&dev->ohci_mmio_mapping, 0, 0x1000,
|
|
ohci_mmio_read, ohci_mmio_readw, ohci_mmio_readl,
|
|
ohci_mmio_write, ohci_mmio_writew, ohci_mmio_writel,
|
|
NULL, MEM_MAPPING_EXTERNAL, dev);
|
|
|
|
mem_mapping_disable(&dev->ohci_mmio_mapping);
|
|
|
|
timer_add(&dev->ohci_frame_timer, ohci_update_frame_counter, dev, 0); /* Unused for now, to be used for frame counting. */
|
|
timer_add(&dev->ohci_port_reset_timer[0], ohci_port_reset_callback, dev, 0);
|
|
timer_add(&dev->ohci_port_reset_timer[1], ohci_port_reset_callback_2, dev, 0);
|
|
timer_add(&dev->ohci_interrupt_desc_poll_timer, ohci_poll_interrupt_descriptors, dev, 0);
|
|
|
|
usb_reset(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t usb_device = {
|
|
.name = "Universal Serial Bus",
|
|
.internal_name = "usb",
|
|
.flags = DEVICE_PCI | DEVICE_EXTPARAMS,
|
|
.local = 0,
|
|
.init_ext = usb_init_ext,
|
|
.close = usb_close,
|
|
.reset = usb_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|