6802c0593b
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically. 2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo. 3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x). 4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12). 5. Preliminary (and incomplete) 4bpp XGA mode. 6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection. 7. Small ROP fixes to both XGA and 8514/A. 8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems. 9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly. 10. Remove useless and crashy bios-less option of the Trantor T128. 11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30). 12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
539 lines
18 KiB
C
539 lines
18 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Header of the code common to the AHA-154x series of SCSI
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* Host Adapters made by Adaptec, Inc. and the BusLogic series
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* of SCSI Host Adapters made by Mylex.
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* These controllers were designed for various buses.
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*
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*
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*
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* Authors: TheCollector1995, <mariogplayer@gmail.com>
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* Miran Grca, <mgrca8@gmail.com>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2016-2018 Miran Grca.
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* Copyright 2017-2018 Fred N. van Kempen.
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*/
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#ifndef SCSI_X54X_H
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#define SCSI_X54X_H
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#define SCSI_DELAY_TM 1 /* was 50 */
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#define ROM_SIZE 16384 /* one ROM is 16K */
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#define NVR_SIZE 256 /* size of NVR */
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/* EEPROM map and bit definitions. */
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#define EE0_HOSTID 0x07 /* EE(0) [2:0] */
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#define EE0_ALTFLOP 0x80 /* EE(0) [7] FDC at 370h */
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#define EE1_IRQCH 0x07 /* EE(1) [3:0] */
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#define EE1_DMACH 0x70 /* EE(1) [7:4] */
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#define EE2_RMVOK 0x01 /* EE(2) [0] Support removable disks */
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#define EE2_HABIOS 0x02 /* EE(2) [1] HA Bios Space Reserved */
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#define EE2_INT19 0x04 /* EE(2) [2] HA Bios Controls INT19 */
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#define EE2_DYNSCAN 0x08 /* EE(2) [3] Dynamically scan bus */
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#define EE2_TWODRV 0x10 /* EE(2) [4] Allow more than 2 drives */
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#define EE2_SEEKRET 0x20 /* EE(2) [5] Immediate return on seek */
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#define EE2_EXT1G 0x80 /* EE(2) [7] Extended Translation >1GB */
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#define EE3_SPEED 0x00 /* EE(3) [7:0] DMA Speed */
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#define SPEED_33 0xFF
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#define SPEED_50 0x00
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#define SPEED_56 0x04
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#define SPEED_67 0x01
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#define SPEED_80 0x02
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#define SPEED_10 0x03
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#define EE4_FLOPTOK 0x80 /* EE(4) [7] Support Flopticals */
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#define EE6_PARITY 0x01 /* EE(6) [0] parity check enable */
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#define EE6_TERM 0x02 /* EE(6) [1] host term enable */
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#define EE6_RSTBUS 0x04 /* EE(6) [2] reset SCSI bus on boot */
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#define EEE_SYNC 0x01 /* EE(E) [0] Enable Sync Negotiation */
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#define EEE_DISCON 0x02 /* EE(E) [1] Enable Disconnection */
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#define EEE_FAST 0x04 /* EE(E) [2] Enable FAST SCSI */
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#define EEE_START 0x08 /* EE(E) [3] Enable Start Unit */
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/*
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* Host Adapter I/O ports.
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*
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* READ Port x+0: STATUS
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* WRITE Port x+0: CONTROL
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*
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* READ Port x+1: DATA
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* WRITE Port x+1: COMMAND
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*
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* READ Port x+2: INTERRUPT STATUS
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* WRITE Port x+2: (undefined?)
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*
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* R/W Port x+3: (undefined)
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*/
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/* WRITE CONTROL commands. */
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#define CTRL_HRST 0x80 /* Hard reset */
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#define CTRL_SRST 0x40 /* Soft reset */
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#define CTRL_IRST 0x20 /* interrupt reset */
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#define CTRL_SCRST 0x10 /* SCSI bus reset */
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/* READ STATUS. */
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#define STAT_STST 0x80 /* self-test in progress */
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#define STAT_DFAIL 0x40 /* internal diagnostic failure */
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#define STAT_INIT 0x20 /* mailbox initialization required */
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#define STAT_IDLE 0x10 /* HBA is idle */
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#define STAT_CDFULL 0x08 /* Command/Data output port is full */
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#define STAT_DFULL 0x04 /* Data input port is full */
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#define STAT_INVCMD 0x01 /* Invalid command */
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/* READ/WRITE DATA. */
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#define CMD_NOP 0x00 /* No operation */
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#define CMD_MBINIT 0x01 /* mailbox initialization */
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#define CMD_START_SCSI 0x02 /* Start SCSI command */
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#define CMD_BIOSCMD 0x03 /* Execute ROM BIOS command */
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#define CMD_INQUIRY 0x04 /* Adapter inquiry */
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#define CMD_EMBOI 0x05 /* enable Mailbox Out Interrupt */
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#define CMD_SELTIMEOUT 0x06 /* Set SEL timeout */
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#define CMD_BUSON_TIME 0x07 /* set bus-On time */
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#define CMD_BUSOFF_TIME 0x08 /* set bus-off time */
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#define CMD_DMASPEED 0x09 /* set ISA DMA speed */
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#define CMD_RETDEVS 0x0A /* return installed devices */
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#define CMD_RETCONF 0x0B /* return configuration data */
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#define CMD_TARGET 0x0C /* set HBA to target mode */
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#define CMD_RETSETUP 0x0D /* return setup data */
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#define CMD_WRITE_CH2 0x1A /* write channel 2 buffer */
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#define CMD_READ_CH2 0x1B /* read channel 2 buffer */
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#define CMD_ECHO 0x1F /* ECHO command data */
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#define CMD_OPTIONS 0x21 /* set adapter options */
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/* READ INTERRUPT STATUS. */
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#define INTR_ANY 0x80 /* any interrupt */
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#define INTR_SRCD 0x08 /* SCSI reset detected */
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#define INTR_HACC 0x04 /* HA command complete */
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#define INTR_MBOA 0x02 /* MBO empty */
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#define INTR_MBIF 0x01 /* MBI full */
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#define ADDR_TO_U32(x) (((x).hi << 16) | ((x).mid << 8) | ((x).lo & 0xFF))
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#define U32_TO_ADDR(a, x) \
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do { \
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(a).hi = (x) >> 16; \
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(a).mid = (x) >> 8; \
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(a).lo = (x) &0xFF; \
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} while (0)
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/*
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* Mailbox Definitions.
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*
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* Mailbox Out (MBO) command values.
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*/
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#define MBO_FREE 0x00
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#define MBO_START 0x01
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#define MBO_ABORT 0x02
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/* Mailbox In (MBI) status values. */
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#define MBI_FREE 0x00
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#define MBI_SUCCESS 0x01
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#define MBI_ABORT 0x02
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#define MBI_NOT_FOUND 0x03
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#define MBI_ERROR 0x04
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/*
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*
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* CCB - SCSI Command Control Block
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*
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* The CCB is a superset of the CDB (Command Descriptor Block)
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* and specifies detailed information about a SCSI command.
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*
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*/
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/* Byte 0 Command Control Block Operation Code */
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#define SCSI_INITIATOR_COMMAND 0x00
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#define TARGET_MODE_COMMAND 0x01
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#define SCATTER_GATHER_COMMAND 0x02
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#define SCSI_INITIATOR_COMMAND_RES 0x03
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#define SCATTER_GATHER_COMMAND_RES 0x04
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#define BUS_RESET 0x81
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/* Byte 1 Address and Direction Control */
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#define CCB_TARGET_ID_SHIFT 0x06 /* CCB Op Code = 00, 02 */
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#define CCB_INITIATOR_ID_SHIFT 0x06 /* CCB Op Code = 01 */
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#define CCB_DATA_XFER_IN 0x01
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#define CCB_DATA_XFER_OUT 0x02
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#define CCB_LUN_MASK 0x07 /* Logical Unit Number */
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/* Byte 2 SCSI_Command_Length - Length of SCSI CDB
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Byte 3 Request Sense Allocation Length */
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#define FOURTEEN_BYTES 0x00 /* Request Sense Buffer size */
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#define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */
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/* Bytes 4, 5 and 6 Data Length - Data transfer byte count */
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/* Bytes 7, 8 and 9 Data Pointer - SGD List or Data Buffer */
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/* Bytes 10, 11 and 12 Link Pointer - Next CCB in Linked List */
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/* Byte 13 Command Link ID - TBD (I don't know yet) */
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/* Byte 14 Host Status - Host Adapter status */
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#define CCB_COMPLETE 0x00 /* CCB completed without error */
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#define CCB_LINKED_COMPLETE 0x0A /* Linked command completed */
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#define CCB_LINKED_COMPLETE_INT 0x0B /* Linked complete with intr */
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#define CCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */
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#define CCB_DATA_OVER_UNDER_RUN 0x12
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#define CCB_UNEXPECTED_BUS_FREE 0x13 /* Trg dropped SCSI BSY */
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#define CCB_PHASE_SEQUENCE_FAIL 0x14 /* Trg bus phase sequence fail */
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#define CCB_BAD_MBO_COMMAND 0x15 /* MBO command not 0, 1 or 2 */
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#define CCB_INVALID_OP_CODE 0x16 /* CCB invalid operation code */
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#define CCB_BAD_LINKED_LUN 0x17 /* Linked CCB LUN diff from 1st */
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#define CCB_INVALID_DIRECTION 0x18 /* Invalid target direction */
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#define CCB_DUPLICATE_CCB 0x19 /* Duplicate CCB */
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#define CCB_INVALID_CCB 0x1A /* Invalid CCB - bad parameter */
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#define lba32_blk(p) ((uint32_t) (p->u.lba.lba0 << 24) | (p->u.lba.lba1 << 16) | (p->u.lba.lba2 << 8) | p->u.lba.lba3)
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/*
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*
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* Scatter/Gather Segment List Definitions
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*
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* Adapter limits
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*/
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#define MAX_SG_DESCRIPTORS 32 /* Always make the array 32 elements long, if less are used, that's not an issue. */
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#pragma pack(push, 1)
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typedef struct addr24_s {
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uint8_t hi;
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uint8_t mid;
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uint8_t lo;
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} addr24_t;
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/* Structure for the INQUIRE_SETUP_INFORMATION reply. */
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typedef struct ReplyInquireSetupInformationSynchronousValue_t {
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uint8_t uOffset : 4;
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uint8_t uTransferPeriod : 3;
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uint8_t fSynchronous : 1;
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} ReplyInquireSetupInformationSynchronousValue;
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typedef struct ReplyInquireSetupInformation_t {
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uint8_t fSynchronousInitiationEnabled : 1;
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uint8_t fParityCheckingEnabled : 1;
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uint8_t uReserved1 : 6;
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uint8_t uBusTransferRate;
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uint8_t uPreemptTimeOnBus;
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uint8_t uTimeOffBus;
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uint8_t cMailbox;
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addr24_t MailboxAddress;
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ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];
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uint8_t uDisconnectPermittedId0To7;
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uint8_t VendorSpecificData[28];
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} ReplyInquireSetupInformation;
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typedef struct MailboxInit_t {
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uint8_t Count;
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addr24_t Address;
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} MailboxInit_t;
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typedef struct Mailbox_t {
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uint8_t CmdStatus;
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addr24_t CCBPointer;
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} Mailbox_t;
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typedef struct Mailbox32_t {
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uint32_t CCBPointer;
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union {
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struct out_t {
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uint8_t Reserved[3];
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uint8_t ActionCode;
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} out;
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struct in_t {
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uint8_t HostStatus;
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uint8_t TargetStatus;
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uint8_t Reserved;
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uint8_t CompletionCode;
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} in;
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} u;
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} Mailbox32_t;
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/* Byte 15 Target Status
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See scsi.h files for these statuses.
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Bytes 16 and 17 Reserved (must be 0)
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Bytes 18 through 18+n-1, where n=size of CDB Command Descriptor Block */
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typedef struct CCB32_t {
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uint8_t Opcode;
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uint8_t Reserved1 : 3;
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uint8_t ControlByte : 2;
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uint8_t TagQueued : 1;
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uint8_t QueueTag : 2;
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uint8_t CdbLength;
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uint8_t RequestSenseLength;
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uint32_t DataLength;
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uint32_t DataPointer;
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uint8_t Reserved2[2];
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uint8_t HostStatus;
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uint8_t TargetStatus;
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uint8_t Id;
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uint8_t Lun : 5;
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uint8_t LegacyTagEnable : 1;
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uint8_t LegacyQueueTag : 2;
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uint8_t Cdb[12];
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uint8_t Reserved3[6];
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uint32_t SensePointer;
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} CCB32;
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typedef struct CCB_t {
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uint8_t Opcode;
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uint8_t Lun : 3;
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uint8_t ControlByte : 2;
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uint8_t Id : 3;
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uint8_t CdbLength;
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uint8_t RequestSenseLength;
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addr24_t DataLength;
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addr24_t DataPointer;
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addr24_t LinkPointer;
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uint8_t LinkId;
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uint8_t HostStatus;
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uint8_t TargetStatus;
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uint8_t Reserved[2];
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uint8_t Cdb[12];
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} CCB;
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typedef struct CCBC_t {
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uint8_t Opcode;
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uint8_t Pad1 : 3;
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uint8_t ControlByte : 2;
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uint8_t Pad2 : 3;
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uint8_t CdbLength;
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uint8_t RequestSenseLength;
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uint8_t Pad3[9];
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uint8_t CompletionCode; /* Only used by the 1542C/CF(/CP?) BIOS mailboxes */
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uint8_t HostStatus;
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uint8_t TargetStatus;
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uint8_t Pad4[2];
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uint8_t Cdb[12];
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} CCBC;
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typedef union CCBU_t {
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CCB32 new;
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CCB old;
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CCBC common;
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} CCBU;
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typedef struct {
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CCBU CmdBlock;
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uint8_t *RequestSenseBuffer;
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uint32_t CCBPointer;
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int Is24bit;
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uint8_t TargetID;
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uint8_t LUN;
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uint8_t HostStatus;
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uint8_t TargetStatus;
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uint8_t MailboxCompletionCode;
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} Req_t;
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typedef struct BIOSCMD_t {
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uint8_t command;
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uint8_t lun : 3;
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uint8_t reserved : 2;
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uint8_t id : 3;
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union {
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struct chs_t {
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uint16_t cyl;
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uint8_t head;
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uint8_t sec;
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} chs;
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struct lba_t {
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uint8_t lba0; /* MSB */
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uint8_t lba1;
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uint8_t lba2;
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uint8_t lba3; /* LSB */
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} lba;
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} u;
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uint8_t secount;
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addr24_t dma_address;
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} BIOSCMD;
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typedef struct SGE32_t {
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uint32_t Segment;
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uint32_t SegmentPointer;
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} SGE32;
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typedef struct SGE_t {
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addr24_t Segment;
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addr24_t SegmentPointer;
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} SGE;
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#pragma pack(pop)
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#define X54X_CDROM_BOOT 1
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#define X54X_32BIT 2
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#define X54X_LBA_BIOS 4
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#define X54X_INT_GEOM_WRITABLE 8
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#define X54X_MBX_24BIT 16
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#define X54X_ISAPNP 32
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#define X54X_HAS_SIGNATURE 64
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typedef struct x54x_t {
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/* 32 bytes */
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char vendor[16]; /* name of device vendor */
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char name[16]; /* name of device */
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/* 24 bytes */
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int8_t type; /* type of device */
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int8_t IrqEnabled;
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int8_t Irq;
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int8_t DmaChannel;
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int8_t HostID;
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uint8_t callback_phase : 4;
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uint8_t callback_sub_phase : 4;
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uint8_t scsi_cmd_phase;
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uint8_t bus;
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uint8_t sync;
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uint8_t parity;
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uint8_t shram_mode;
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uint8_t Geometry;
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uint8_t Control;
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uint8_t Command;
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uint8_t CmdParam;
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uint8_t BusOnTime;
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uint8_t BusOffTime;
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uint8_t ATBusSpeed;
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uint8_t setup_info_len;
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uint8_t max_id;
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uint8_t pci_slot;
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uint8_t irq_state;
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uint8_t pad;
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uint8_t pad0;
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uint8_t pad1;
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uint8_t temp_cdb[12];
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/* for multi-threading, keep these volatile */
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volatile uint8_t Status;
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volatile uint8_t Interrupt;
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volatile uint8_t MailboxIsBIOS;
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volatile uint8_t ToRaise;
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volatile uint8_t flags;
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/* 65928 bytes */
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uint8_t pos_regs[8]; /* MCA */
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uint8_t CmdBuf[128];
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uint8_t DataBuf[65536];
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uint8_t shadow_ram[128];
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uint8_t dma_buffer[128];
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uint8_t cmd_33_buf[4096];
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/* 16 bytes */
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char *fw_rev; /* The 4 bytes of the revision command information + 2 extra bytes for BusLogic */
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uint8_t *rom1; /* main BIOS image */
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uint8_t *rom2; /* SCSI-Select image */
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uint8_t *nvr; /* EEPROM buffer */
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/* 6 words = 12 bytes */
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uint16_t DataReply;
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uint16_t DataReplyLeft;
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uint16_t rom_ioaddr; /* offset in BIOS of I/O addr */
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uint16_t rom_shram; /* index to shared RAM */
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uint16_t rom_shramsz; /* size of shared RAM */
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uint16_t rom_fwhigh; /* offset in BIOS of ver ID */
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uint16_t pnp_len; /* length of the PnP ROM */
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uint16_t pnp_offset; /* offset in the microcode ROM of the PnP ROM */
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uint16_t cmd_33_len; /* length of the SCSISelect code decompressor program */
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uint16_t cmd_33_offset; /* offset in the microcode ROM of the SCSISelect code decompressor program */
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/* 16 + 20 + 52 = 88 bytes */
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volatile int MailboxOutInterrupts;
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|
volatile int PendingInterrupt;
|
|
volatile int Lock;
|
|
volatile int target_data_len;
|
|
volatile int pad2;
|
|
|
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uint32_t Base;
|
|
uint32_t fdc_address;
|
|
uint32_t rom_addr; /* address of BIOS ROM */
|
|
uint32_t CmdParamLeft;
|
|
uint32_t Outgoing;
|
|
uint32_t transfer_size;
|
|
|
|
volatile uint32_t MailboxInit;
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|
volatile uint32_t MailboxCount;
|
|
volatile uint32_t MailboxOutAddr;
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|
volatile uint32_t MailboxOutPosCur;
|
|
volatile uint32_t MailboxInAddr;
|
|
volatile uint32_t MailboxInPosCur;
|
|
volatile uint32_t MailboxReq;
|
|
volatile uint32_t BIOSMailboxInit;
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|
volatile uint32_t BIOSMailboxCount;
|
|
volatile uint32_t BIOSMailboxOutAddr;
|
|
volatile uint32_t BIOSMailboxOutPosCur;
|
|
volatile uint32_t BIOSMailboxReq;
|
|
volatile uint32_t Residue;
|
|
volatile uint32_t card_bus; /* Basically a copy of device flags */
|
|
|
|
/* 8 bytes */
|
|
uint64_t temp_period;
|
|
|
|
/* 16 bytes */
|
|
double media_period;
|
|
double ha_bps; /* bytes per second */
|
|
|
|
/* 8 bytes */
|
|
char *bios_path; /* path to BIOS image file */
|
|
char *mcode_path; /* path to microcode image file, needed by the AHA-1542CP */
|
|
char *nvr_path; /* path to NVR image file */
|
|
|
|
/* 56 bytes */
|
|
/* Pointer to a structure of vendor-specific data that only the vendor-specific code can understand */
|
|
void *ven_data;
|
|
|
|
/* Pointer to a function that performs vendor-specific operation during the timer callback */
|
|
void (*ven_callback)(void *priv);
|
|
/* Pointer to a function that executes the second parameter phase of the vendor-specific command */
|
|
void (*ven_cmd_phase1)(void *priv);
|
|
/* Pointer to a function that gets the host adapter ID in case it has to be read from a non-standard location */
|
|
uint8_t (*ven_get_host_id)(void *priv);
|
|
/* Pointer to a function that updates the IRQ in the vendor-specific space */
|
|
uint8_t (*ven_get_irq)(void *priv);
|
|
/* Pointer to a function that updates the DMA channel in the vendor-specific space */
|
|
uint8_t (*ven_get_dma)(void *priv);
|
|
/* Pointer to a function that returns whether command is fast */
|
|
uint8_t (*ven_cmd_is_fast)(void *priv);
|
|
/* Pointer to a function that executes vendor-specific fast path commands */
|
|
uint8_t (*ven_fast_cmds)(void *priv, uint8_t cmd);
|
|
/* Pointer to a function that gets the parameter length for vendor-specific commands */
|
|
uint8_t (*get_ven_param_len)(void *priv);
|
|
/* Pointer to a function that executes vendor-specific commands and returns whether or not to suppress the IRQ */
|
|
uint8_t (*ven_cmds)(void *priv);
|
|
/* Pointer to a function that fills in the vendor-specific setup data */
|
|
void (*get_ven_data)(void *priv);
|
|
/* Pointer to a function that determines if the mode is aggressive */
|
|
uint8_t (*is_aggressive_mode)(void *priv);
|
|
/* Pointer to a function that returns interrupt type (0 = edge, 1 = level) */
|
|
uint8_t (*interrupt_type)(void *priv);
|
|
/* Pointer to a function that resets vendor-specific data */
|
|
void (*ven_reset)(void *priv);
|
|
|
|
rom_t bios; /* BIOS memory descriptor */
|
|
rom_t uppersck; /* BIOS memory descriptor */
|
|
|
|
mem_mapping_t mmio_mapping;
|
|
|
|
pc_timer_t timer;
|
|
pc_timer_t ResetCB;
|
|
|
|
Req_t Req;
|
|
|
|
fdc_t *fdc;
|
|
} x54x_t;
|
|
|
|
extern void x54x_reset_ctrl(x54x_t *dev, uint8_t Reset);
|
|
extern uint8_t x54x_mbo_process(x54x_t *dev);
|
|
extern void x54x_wait_for_poll(void);
|
|
extern void x54x_io_set(x54x_t *dev, uint32_t base, uint8_t len);
|
|
extern void x54x_io_remove(x54x_t *dev, uint32_t base, uint8_t len);
|
|
extern void x54x_mem_init(x54x_t *dev, uint32_t addr);
|
|
extern void x54x_mem_enable(x54x_t *dev);
|
|
extern void x54x_mem_set_addr(x54x_t *dev, uint32_t base);
|
|
extern void x54x_mem_disable(x54x_t *dev);
|
|
extern void *x54x_init(const device_t *info);
|
|
extern void x54x_close(void *priv);
|
|
extern void x54x_device_reset(void *priv);
|
|
|
|
#endif
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