330 lines
9.0 KiB
C
330 lines
9.0 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the Brooktree BT485 and BT485A true colour
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* RAM DAC's.
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*
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* Version: @(#)vid_bt485_ramdac.c 1.0.9 2018/10/03
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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* TheCollector1995,
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*
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* Copyright 2016-2018 Miran Grca.
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* Copyright 2018 TheCollector1995.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../mem.h"
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#include "video.h"
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#include "vid_svga.h"
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#include "vid_bt485_ramdac.h"
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static void
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bt485_set_bpp(bt485_ramdac_t *ramdac, svga_t *svga)
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{
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if (!(ramdac->cr2 & 0x20))
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svga->bpp = 8;
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else switch ((ramdac->cr1 >> 5) & 0x03) {
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case 0:
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svga->bpp = 32;
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break;
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case 1:
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if (ramdac->cr1 & 0x08)
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svga->bpp = 16;
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else
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svga->bpp = 15;
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break;
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case 2:
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svga->bpp = 8;
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break;
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case 3:
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svga->bpp = 4;
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break;
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}
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svga_recalctimings(svga);
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}
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void
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bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *ramdac, svga_t *svga)
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{
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uint32_t o32;
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uint8_t *cd;
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uint8_t index;
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uint8_t rs = (addr & 0x03);
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rs |= (!!rs2 << 2);
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rs |= (!!rs3 << 3);
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switch (rs) {
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case 0x00: /* Palette Write Index Register (RS value = 0000) */
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case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
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svga_out(addr, val, svga);
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if ((ramdac->type >= BT485) && (svga->hwcursor.xsize == 64))
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svga->dac_write |= ((int) (ramdac->cr3 & 0x03) << 8);
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break;
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case 0x01: /* Palette Data Register (RS value = 0001) */
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case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
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case 0x03: /* Palette Read Index Register (RS value = 0011) */
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case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
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svga_out(addr, val, svga);
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break;
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case 0x05: /* Ext Palette Data Register (RS value = 0101) */
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svga->dac_status = 0;
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svga->fullchange = changeframecount;
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switch (svga->dac_pos) {
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case 0:
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svga->dac_r = val;
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svga->dac_pos++;
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break;
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case 1:
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svga->dac_g = val;
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svga->dac_pos++;
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break;
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case 2:
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index = svga->dac_write & 3;
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ramdac->extpal[index].r = svga->dac_r;
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ramdac->extpal[index].g = svga->dac_g;
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ramdac->extpal[index].b = val;
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if (svga->ramdac_type == RAMDAC_8BIT)
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ramdac->extpallook[index] = makecol32(ramdac->extpal[index].r, ramdac->extpal[index].g, ramdac->extpal[index].b);
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else
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ramdac->extpallook[index] = makecol32(video_6to8[ramdac->extpal[index].r & 0x3f], video_6to8[ramdac->extpal[index].g & 0x3f], video_6to8[ramdac->extpal[index].b & 0x3f]);
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if ((svga->crtc[0x33] & 0x40) && !index) {
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o32 = svga->overscan_color;
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svga->overscan_color = ramdac->extpallook[0];
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if (o32 != svga->overscan_color)
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svga_recalctimings(svga);
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}
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svga->dac_write = (svga->dac_write + 1);
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svga->dac_pos = 0;
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break;
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}
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break;
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case 0x06: /* Command Register 0 (RS value = 0110) */
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ramdac->cr0 = val;
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svga->ramdac_type = (val & 0x02) ? RAMDAC_8BIT : RAMDAC_6BIT;
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break;
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case 0x08: /* Command Register 1 (RS value = 1000) */
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ramdac->cr1 = val;
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bt485_set_bpp(ramdac, svga);
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break;
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case 0x09: /* Command Register 2 (RS value = 1001) */
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ramdac->cr2 = val;
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svga->hwcursor.ena = !!(val & 0x03);
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bt485_set_bpp(ramdac, svga);
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break;
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case 0x0a:
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if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) {
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switch ((svga->dac_write & 0xff)) {
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case 0x01:
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/* Command Register 3 (RS value = 1010) */
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ramdac->cr3 = val;
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svga->hwcursor.xsize = svga->hwcursor.ysize = (val & 4) ? 64 : 32;
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svga->hwcursor.yoff = (svga->hwcursor.ysize == 32) ? 32 : 0;
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svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
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svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
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if (svga->hwcursor.xsize == 64)
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svga->dac_write = (svga->dac_write & 0x00ff) | ((val & 0x03) << 8);
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svga_recalctimings(svga);
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break;
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case 0x02:
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case 0x20:
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case 0x21:
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case 0x22:
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if (ramdac->type != BT485A)
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break;
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else if (svga->dac_write == 2) {
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ramdac->cr4 = val;
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break;
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}
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break;
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}
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}
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break;
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case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
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if (svga->hwcursor.xsize == 64)
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cd = (uint8_t *) ramdac->cursor64_data;
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else
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cd = (uint8_t *) ramdac->cursor32_data;
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cd[svga->dac_write] = val;
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svga->dac_write++;
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svga->dac_write &= ((svga->hwcursor.xsize == 64) ? 0x03ff : 0x00ff);
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break;
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case 0x0c: /* Cursor X Low Register (RS value = 1100) */
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ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
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svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
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break;
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case 0x0d: /* Cursor X High Register (RS value = 1101) */
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ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | ((val & 0x0f) << 8);
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svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
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break;
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case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
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ramdac->hwc_y = (ramdac->hwc_y & 0x0f00) | val;
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svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
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break;
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case 0x0f: /* Cursor Y High Register (RS value = 1111) */
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ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | ((val & 0x0f) << 8);
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svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
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break;
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}
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return;
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}
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uint8_t
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bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t *svga)
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{
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uint8_t temp = 0xff;
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uint8_t *cd;
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uint8_t index;
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uint8_t rs = (addr & 0x03);
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rs |= (!!rs2 << 2);
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rs |= (!!rs3 << 3);
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switch (rs) {
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case 0x00: /* Palette Write Index Register (RS value = 0000) */
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case 0x01: /* Palette Data Register (RS value = 0001) */
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case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
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case 0x03: /* Palette Read Index Register (RS value = 0011) */
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case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
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case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
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temp = svga_in(addr, svga);
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break;
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case 0x05: /* Ext Palette Data Register (RS value = 0101) */
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index = svga->dac_read & 3;
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svga->dac_status = 3;
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switch (svga->dac_pos) {
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case 0:
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svga->dac_pos++;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].r;
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else
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temp = ramdac->extpal[index].r & 0x3f;
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case 1:
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svga->dac_pos++;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].g;
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else
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temp = ramdac->extpal[index].g & 0x3f;
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case 2:
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svga->dac_pos=0;
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svga->dac_read = svga->dac_read + 1;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].b;
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else
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temp = ramdac->extpal[index].b & 0x3f;
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}
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break;
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case 0x06: /* Command Register 0 (RS value = 0110) */
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temp = ramdac->cr0;
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break;
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case 0x08: /* Command Register 1 (RS value = 1000) */
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temp = ramdac->cr1;
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break;
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case 0x09: /* Command Register 2 (RS value = 1001) */
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temp = ramdac->cr2;
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break;
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case 0x0a:
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if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) {
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switch ((svga->dac_write & 0xff)) {
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case 0x00:
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temp = ramdac->status;
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break;
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case 0x01:
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temp = ramdac->cr3;
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break;
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case 0x02:
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case 0x20:
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case 0x21:
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case 0x22:
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if (ramdac->type != BT485A)
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break;
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else if (svga->dac_write == 2) {
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temp = ramdac->cr4;
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break;
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} else {
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/* TODO: Red, Green, and Blue Signature Analysis Registers */
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temp = 0xff;
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break;
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}
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break;
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}
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} else
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temp = ramdac->status;
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break;
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case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
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if (svga->hwcursor.xsize == 64)
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cd = (uint8_t *) ramdac->cursor64_data;
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else
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cd = (uint8_t *) ramdac->cursor32_data;
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temp = cd[svga->dac_write];
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svga->dac_write++;
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svga->dac_write &= ((svga->hwcursor.xsize == 64) ? 0x03ff : 0x00ff);
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break;
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case 0x0c: /* Cursor X Low Register (RS value = 1100) */
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temp = ramdac->hwc_x & 0xff;
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break;
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case 0x0d: /* Cursor X High Register (RS value = 1101) */
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temp = (ramdac->hwc_x >> 8) & 0xff;
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break;
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case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
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temp = ramdac->hwc_y & 0xff;
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break;
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case 0x0f: /* Cursor Y High Register (RS value = 1111) */
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temp = (ramdac->hwc_y >> 8) & 0xff;
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break;
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}
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return temp;
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}
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void bt485_init(bt485_ramdac_t *ramdac, svga_t *svga, uint8_t type)
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{
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memset(ramdac, 0, sizeof(bt485_ramdac_t));
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ramdac->type = type;
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if (ramdac->type < BT485) {
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/* The BT484 and AT&T 20C504 only have a 32x32 cursor. */
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svga->hwcursor.xsize = svga->hwcursor.ysize = 32;
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svga->hwcursor.yoff = 32;
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}
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/* Set the RAM DAC status byte to the correct ID bits.
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Both the BT484 and BT485 datasheets say this:
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SR7-SR6: These bits are identification values. SR7=0 and SR6=1.
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But all other sources seem to assume SR7=1 and SR6=0. */
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switch (ramdac->type) {
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case BT484:
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ramdac->status = 0x40;
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break;
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case ATT20C504:
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ramdac->status = 0x40;
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break;
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case BT485:
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ramdac->status = 0x60;
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break;
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case ATT20C505:
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ramdac->status = 0xd0;
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break;
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case BT485A:
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ramdac->status = 0x20;
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break;
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}
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}
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