252 lines
5.6 KiB
C
252 lines
5.6 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the UMC HB4 "Super Energy Star Green" PCI Chipset.
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*
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* Note: This chipset has no datasheet, everything were done via
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* reverse engineering the BIOS of various machines using it.
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*
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* Note 2: Additional information were also used from all
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* around the web.
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*
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* Authors: Tiseno100,
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*
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* Copyright 2021 Tiseno100.
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*/
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/*
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UMC HB4 Configuration Registers
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Sources & Notes:
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Cache registers were found at Vogons: https://www.vogons.org/viewtopic.php?f=46&t=68829&start=20
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Basic Reverse engineering effort was done personally by me
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TODO:
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- APM, SMM, SMRAM registers(Did some early work. Still quite incomplete)
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- More Appropriate Bitmasking(If it's even possible)
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Warning: Register documentation may be inaccurate!
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UMC 8881x:
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Register 50:
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Bit 7: Enable L2 Cache
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Bit 6: Cache Policy (0: Write Thru / 1: Write Back)
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Bit 5-4 Cache Speed
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0 0 Read 3-2-2-2 Write 3T
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0 1 Read 3-1-1-1 Write 3T
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1 0 Read 2-2-2-2 Write 2T
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1 1 Read 2-1-1-1 Write 2T
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Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
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Bit 2-1-0 Cache Size
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0 0 0 0KB
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0 0 1 64KB
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x-x-x Multiplications of 2(64*2 for 0 1 0) till 2MB
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Register 51:
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Bit 7-6 DRAM Read Speed
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5-4 DRAM Write Speed
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0 0 1 Waits
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0 1 1 Waits
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1 0 1 Wait
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1 1 0 Waits
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Bit 3 Resource Lock Enable
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Bit 2 Graphics Adapter (0: VL Bus / 1: PCI Bus)
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Bit 1 L1 WB Policy (0: WT / 1: WB)
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Bit 0 L2 Cache Tag Lenght (0: 7 Bits / 1: 8 Bits)
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Register 52:
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Bit 7: Host-to-PCI Post Write (0: 1 Wait State / 1: 0 Wait States)
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Register 54:
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Bit 7: DC000-DFFFF
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Bit 6: D8000-DBFFF
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Bit 5: D4000-D7FFF
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Bit 4: D0000-D3FFF
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Bit 3: CC000-CFFFF
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Bit 2: C8000-CBFFF
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Bit 1: C0000-C7FFF
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Bit 0: Reserved
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Register 55:
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Bit 7: Enable Shadow Reads For System & Selected Segments
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Bit 6: Write Protect Enable
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/apm.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/port_92.h>
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#include <86box/smram.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_HB4_LOG
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int hb4_do_log = ENABLE_HB4_LOG;
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static void
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hb4_log(const char *fmt, ...)
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{
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va_list ap;
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if (hb4_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define hb4_log(fmt, ...)
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#endif
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/* Shadow RAM Flags */
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#define CAN_READ ((dev->pci_conf[0x55] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
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#define CAN_WRITE ((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)
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#define DISABLE (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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typedef struct hb4_t
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{
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apm_t *apm;
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smram_t *smram;
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uint8_t pci_conf[256]; /* PCI Registers */
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} hb4_t;
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void hb4_shadow(int cur_addr, hb4_t *dev)
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{
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mem_set_mem_state_both(0xc0000, 0x8000, (dev->pci_conf[0x54] & 2) ? (CAN_READ | CAN_WRITE) : DISABLE);
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for (int i = 2; i < 8; i++)
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mem_set_mem_state_both(0xc8000 + ((i - 2) << 14), 0x4000, (dev->pci_conf[0x54] & (1 << i)) ? (CAN_READ | CAN_WRITE) : DISABLE);
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mem_set_mem_state_both(0xe0000, 0x20000, CAN_READ | CAN_WRITE);
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flushmmucache_nopc();
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}
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static void
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um8881_write(int func, int addr, uint8_t val, void *priv)
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{
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hb4_t *dev = (hb4_t *)priv;
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hb4_log("UM8881: dev->regs[%02x] = %02x\n", addr, val);
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if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
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switch (addr)
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{
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case 0x50:
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dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
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cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/
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cpu_update_waitstates();
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break;
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case 0x54:
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case 0x55:
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dev->pci_conf[addr] = val & (!(addr & 1) ? 0xfe : 0xff);
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hb4_shadow(addr, dev);
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break;
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case 0x60:
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dev->pci_conf[addr] = val & 0x3f;
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break;
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case 0x61:
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dev->pci_conf[addr] = val & 0x0f;
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break;
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default:
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dev->pci_conf[addr] = val;
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break;
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}
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}
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static uint8_t
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um8881_read(int func, int addr, void *priv)
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{
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hb4_t *dev = (hb4_t *)priv;
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return dev->pci_conf[addr];
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}
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static void
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hb4_reset(void *priv)
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{
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hb4_t *dev = (hb4_t *)priv;
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/* Defaults */
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dev->pci_conf[0] = 0x60; /* UMC */
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dev->pci_conf[1] = 0x10;
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dev->pci_conf[2] = 0x81; /* 8881x */
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dev->pci_conf[3] = 0x88;
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dev->pci_conf[8] = 1;
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dev->pci_conf[0x09] = 0x00;
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dev->pci_conf[0x0a] = 0x00;
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dev->pci_conf[0x0b] = 0x06;
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}
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static void
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hb4_close(void *priv)
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{
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hb4_t *dev = (hb4_t *)priv;
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//smram_del(dev->smram);
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free(dev);
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}
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static void *
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hb4_init(const device_t *info)
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{
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hb4_t *dev = (hb4_t *)malloc(sizeof(hb4_t));
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memset(dev, 0, sizeof(hb4_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, um8881_read, um8881_write, dev); /* Device 10: UMC 8881x */
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/* APM */
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dev->apm = device_add(&apm_pci_device);
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/* SMRAM(Needs excessive documentation before we begin SMM implementation) */
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//dev->smram = smram_add();
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/* Port 92 */
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device_add(&port_92_pci_device);
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hb4_reset(dev);
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return dev;
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}
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const device_t umc_hb4_device = {
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"UMC HB4(8881F)",
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DEVICE_PCI,
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0x886a,
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hb4_init,
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hb4_close,
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hb4_reset,
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{NULL},
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NULL,
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NULL,
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NULL};
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