dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
165 lines
3.6 KiB
C
165 lines
3.6 KiB
C
/* Copyright holders: Sarah Walker, Tenshi, leilei
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see COPYING for more details
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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extern int cpu, cpu_manufacturer;
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/*808x class CPUs*/
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#define CPU_8088 0
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#define CPU_8086 1
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/*286 class CPUs*/
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#define CPU_286 2
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/*386 class CPUs*/
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#define CPU_386SX 3
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#define CPU_386DX 4
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#define CPU_RAPIDCAD 5
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#define CPU_486SLC 6
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#define CPU_486DLC 7
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/*486 class CPUs*/
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#define CPU_i486SX 8
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#define CPU_Am486SX 9
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#define CPU_Cx486S 10
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#define CPU_i486DX 11
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#define CPU_Am486DX 12
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#define CPU_Cx486DX 13
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#define CPU_Cx5x86 14
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/*586 class CPUs*/
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#define CPU_WINCHIP 15
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#define CPU_PENTIUM 16
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#define CPU_PENTIUMMMX 17
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#define CPU_Cx6x86 18
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#define CPU_Cx6x86MX 19
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#define CPU_Cx6x86L 20
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#define CPU_CxGX1 21
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#define CPU_K5 22
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#define CPU_5K86 23
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#define CPU_K6 24
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/*686 class CPUs*/
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#define CPU_PENTIUMPRO 25
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/*
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#define CPU_PENTIUM2 26
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#define CPU_PENTIUM2D 27 */
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#define CPU_PENTIUM2D 26
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#define MANU_INTEL 0
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#define MANU_AMD 1
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#define MANU_CYRIX 2
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#define MANU_IDT 3
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extern int timing_rr;
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extern int timing_mr, timing_mrl;
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extern int timing_rm, timing_rml;
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extern int timing_mm, timing_mml;
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extern int timing_bt, timing_bnt;
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extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm, timing_int_pm_outer;
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extern int timing_iret_rm, timing_iret_v86, timing_iret_pm, timing_iret_pm_outer;
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extern int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_gate_inner;
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extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
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extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
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typedef struct
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{
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char name[32];
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int cpu_type;
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int speed;
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int rspeed;
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int multi;
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int pci_speed;
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uint32_t edx_reset;
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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int cpu_flags;
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int mem_read_cycles, mem_write_cycles;
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int cache_read_cycles, cache_write_cycles;
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} CPU;
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extern CPU cpus_8088[];
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extern CPU cpus_8086[];
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extern CPU cpus_286[];
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extern CPU cpus_i386[];
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extern CPU cpus_i386DX[];
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extern CPU cpus_Am386[];
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extern CPU cpus_Am386DX[];
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extern CPU cpus_486SDLC[];
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extern CPU cpus_486DLC[];
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extern CPU cpus_i486[];
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extern CPU cpus_Am486[];
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extern CPU cpus_Cx486[];
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extern CPU cpus_WinChip[];
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extern CPU cpus_Pentium5V[];
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extern CPU cpus_Pentium5V50[];
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extern CPU cpus_PentiumS5[];
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extern CPU cpus_K5[];
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extern CPU cpus_K56[];
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extern CPU cpus_Pentium[];
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extern CPU cpus_6x86[];
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extern CPU cpus_PentiumPro[];
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extern CPU cpus_Pentium2[];
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extern CPU cpus_Pentium2D[];
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extern CPU cpus_pcjr[];
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extern CPU cpus_pc1512[];
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extern CPU cpus_ibmat[];
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extern CPU cpus_ps1_m2011[];
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extern CPU cpus_acer[];
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extern int cpu_iscyrix;
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extern int cpu_16bitbus;
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extern int cpu_busspeed;
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extern int cpu_multi;
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extern int cpu_hasrdtsc;
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extern int cpu_hasMSR;
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extern int cpu_hasMMX;
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extern int cpu_hasCR4;
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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#define CR4_MCE (1 << 6)
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#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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extern uint64_t cpu_CR4_mask;
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#define CPU_SUPPORTS_DYNAREC 1
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#define CPU_REQUIRES_DYNAREC 2
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// #define CPU_REQUIRES_DYNAREC 0
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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extern uint64_t tsc;
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void cyrix_write(uint16_t addr, uint8_t val, void *priv);
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uint8_t cyrix_read(uint16_t addr, void *priv);
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extern int is8086;
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void cpu_CPUID();
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void cpu_RDMSR();
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void cpu_WRMSR();
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extern int cpu_use_dynarec;
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extern int xt_cpu_multi;
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#define ISA_CYCLES_SHIFT 6
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extern int isa_cycles;
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#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
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void cpu_update_waitstates();
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#endif
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