dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
#define INC_DEC_OP(name, reg, inc, setflags) \
|
|
static int op ## name (uint32_t fetchdat) \
|
|
{ \
|
|
setflags(reg, 1); \
|
|
reg += inc; \
|
|
CLOCK_CYCLES(timing_rr); \
|
|
PREFETCH_RUN(timing_rr, 1, -1, 0,0,0,0, 0); \
|
|
return 0; \
|
|
}
|
|
|
|
INC_DEC_OP(INC_AX, AX, 1, setadd16nc)
|
|
INC_DEC_OP(INC_BX, BX, 1, setadd16nc)
|
|
INC_DEC_OP(INC_CX, CX, 1, setadd16nc)
|
|
INC_DEC_OP(INC_DX, DX, 1, setadd16nc)
|
|
INC_DEC_OP(INC_SI, SI, 1, setadd16nc)
|
|
INC_DEC_OP(INC_DI, DI, 1, setadd16nc)
|
|
INC_DEC_OP(INC_BP, BP, 1, setadd16nc)
|
|
INC_DEC_OP(INC_SP, SP, 1, setadd16nc)
|
|
|
|
INC_DEC_OP(INC_EAX, EAX, 1, setadd32nc)
|
|
INC_DEC_OP(INC_EBX, EBX, 1, setadd32nc)
|
|
INC_DEC_OP(INC_ECX, ECX, 1, setadd32nc)
|
|
INC_DEC_OP(INC_EDX, EDX, 1, setadd32nc)
|
|
INC_DEC_OP(INC_ESI, ESI, 1, setadd32nc)
|
|
INC_DEC_OP(INC_EDI, EDI, 1, setadd32nc)
|
|
INC_DEC_OP(INC_EBP, EBP, 1, setadd32nc)
|
|
INC_DEC_OP(INC_ESP, ESP, 1, setadd32nc)
|
|
|
|
INC_DEC_OP(DEC_AX, AX, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_BX, BX, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_CX, CX, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_DX, DX, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_SI, SI, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_DI, DI, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_BP, BP, -1, setsub16nc)
|
|
INC_DEC_OP(DEC_SP, SP, -1, setsub16nc)
|
|
|
|
INC_DEC_OP(DEC_EAX, EAX, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_EBX, EBX, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_ECX, ECX, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_EDX, EDX, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_ESI, ESI, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_EDI, EDI, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_EBP, EBP, -1, setsub32nc)
|
|
INC_DEC_OP(DEC_ESP, ESP, -1, setsub32nc)
|
|
|
|
|
|
static int opINCDEC_b_a16(uint32_t fetchdat)
|
|
{
|
|
uint8_t temp;
|
|
|
|
fetch_ea_16(fetchdat);
|
|
temp=geteab(); if (cpu_state.abrt) return 1;
|
|
|
|
if (rmdat&0x38)
|
|
{
|
|
seteab(temp - 1); if (cpu_state.abrt) return 1;
|
|
setsub8nc(temp, 1);
|
|
}
|
|
else
|
|
{
|
|
seteab(temp + 1); if (cpu_state.abrt) return 1;
|
|
setadd8nc(temp, 1);
|
|
}
|
|
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
|
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
|
|
return 0;
|
|
}
|
|
static int opINCDEC_b_a32(uint32_t fetchdat)
|
|
{
|
|
uint8_t temp;
|
|
|
|
fetch_ea_32(fetchdat);
|
|
temp=geteab(); if (cpu_state.abrt) return 1;
|
|
|
|
if (rmdat&0x38)
|
|
{
|
|
seteab(temp - 1); if (cpu_state.abrt) return 1;
|
|
setsub8nc(temp, 1);
|
|
}
|
|
else
|
|
{
|
|
seteab(temp + 1); if (cpu_state.abrt) return 1;
|
|
setadd8nc(temp, 1);
|
|
}
|
|
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
|
|
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
|
|
return 0;
|
|
}
|