387 lines
10 KiB
C
387 lines
10 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of a generic SiS 5595-compatible SMBus host
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* controller.
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*
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* Authors: RichardG, <richardg867@gmail.com>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020-2021 RichardG.
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/timer.h>
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#include <86box/i2c.h>
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#include <86box/pci.h>
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#include <86box/smbus.h>
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#include <86box/plat_fallthrough.h>
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#ifdef ENABLE_SMBUS_SIS5595_LOG
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int smbus_sis5595_do_log = ENABLE_SMBUS_SIS5595_LOG;
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static void
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smbus_sis5595_log(const char *fmt, ...)
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{
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va_list ap;
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if (smbus_sis5595_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define smbus_sis5595_log(fmt, ...)
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#endif
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static void
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smbus_sis5595_irq(smbus_sis5595_t *dev, int raise)
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{
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if (dev->irq_enable) {
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if (raise)
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pci_set_mirq(6, 1, &dev->irq_state);
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else
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pci_clear_mirq(6, 1, &dev->irq_state);
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}
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}
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void
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smbus_sis5595_irq_enable(void *priv, uint8_t enable)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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if (!enable && dev->irq_enable)
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pci_clear_mirq(6, 1, &dev->irq_state);
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dev->irq_enable = enable;
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}
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uint8_t
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smbus_sis5595_read_index(void *priv)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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return dev->index;
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}
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uint8_t
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smbus_sis5595_read_data(void *priv)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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uint8_t ret = 0x00;
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switch (dev->index) {
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case 0x00:
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ret = dev->stat & 0xff;
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break;
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case 0x01:
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ret = dev->stat >> 8;
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break;
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case 0x02:
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ret = dev->ctl & 0xff;
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break;
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case 0x03:
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ret = dev->ctl >> 8;
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break;
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case 0x04:
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ret = dev->addr;
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break;
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case 0x05:
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ret = dev->cmd;
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break;
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case 0x06:
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ret = dev->block_ptr;
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break;
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case 0x07:
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ret = dev->count;
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break;
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case 0x08 ... 0x0f:
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ret = dev->data[(dev->index & 0x07) + (dev->block_ptr << 3)];
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if (dev->index == 0x0f) {
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dev->block_ptr = (dev->block_ptr + 1) & 3;
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smbus_sis5595_irq(dev, dev->block_ptr != 0x00);
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}
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break;
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case 0x10:
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ret = dev->saved_addr;
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break;
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case 0x11:
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ret = dev->data0;
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break;
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case 0x12:
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ret = dev->data1;
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break;
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case 0x13:
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ret = dev->alias;
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break;
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case 0xff:
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ret = dev->reg_ff & 0xc0;
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break;
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default:
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break;
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}
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smbus_sis5595_log("SMBus SIS5595: read(%02X) = %02x\n", addr, ret);
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return ret;
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}
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void
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smbus_sis5595_write_index(void *priv, uint8_t val)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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dev->index = val;
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}
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void
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smbus_sis5595_write_data(void *priv, uint8_t val)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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uint8_t smbus_addr;
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uint8_t cmd;
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uint8_t read;
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uint16_t prev_stat;
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uint16_t timer_bytes = 0;
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smbus_sis5595_log("SMBus SIS5595: write(%02X, %02X)\n", addr, val);
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prev_stat = dev->next_stat;
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dev->next_stat = 0x0000;
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switch (dev->index) {
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case 0x00:
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dev->stat &= ~(val & 0xf0);
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/* Make sure IDLE is set if we're not busy or errored. */
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if (dev->stat == 0x04)
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dev->stat = 0x00;
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break;
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case 0x01:
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dev->stat &= ~(val & 0x07);
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break;
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case 0x02:
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dev->ctl = (dev->ctl & 0xff00) | val;
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if (val & 0x20) { /* cancel an in-progress command if KILL is set */
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if (prev_stat) { /* cancel only if a command is in progress */
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timer_disable(&dev->response_timer);
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dev->stat = 0x80; /* raise FAILED */
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}
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} else if (val & 0x10) {
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/* dispatch command if START is set */
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timer_bytes++; /* address */
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smbus_addr = (dev->addr >> 1);
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read = dev->addr & 0x01;
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cmd = (dev->ctl >> 1) & 0x7;
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smbus_sis5595_log("SMBus SIS5595: addr=%02X read=%d protocol=%X cmd=%02X "
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"data0=%02X data1=%02X\n", smbus_addr, read, cmd, dev->cmd,
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dev->data0, dev->data1);
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/* Raise DEV_ERR if no device is at this address, or if the device returned
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NAK when starting the transfer. */
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if (!i2c_start(i2c_smbus, smbus_addr, read)) {
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dev->next_stat = 0x0020;
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break;
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}
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dev->next_stat = 0x0040; /* raise INTER (command completed) by default */
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/* Decode the command protocol. */
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dev->block_ptr = 0x01;
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switch (cmd) {
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case 0x0: /* quick R/W */
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break;
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case 0x1: /* byte R/W */
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if (read) /* byte read */
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dev->data[0] = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data[0]);
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timer_bytes++;
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break;
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case 0x2: /* byte data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) /* byte read */
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dev->data[0] = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data[0]);
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timer_bytes++;
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break;
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case 0x3: /* word data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) { /* word read */
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dev->data[0] = i2c_read(i2c_smbus, smbus_addr);
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dev->data[1] = i2c_read(i2c_smbus, smbus_addr);
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} else { /* word write */
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i2c_write(i2c_smbus, smbus_addr, dev->data[0]);
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i2c_write(i2c_smbus, smbus_addr, dev->data[1]);
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}
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timer_bytes += 2;
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break;
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case 0x5: /* block R/W */
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dev->block_ptr = 0x00;
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timer_bytes++; /* count the SMBus length byte now */
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fallthrough;
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default: /* unknown */
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dev->next_stat = 0x0010; /* raise DEV_ERR */
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timer_bytes = 0;
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break;
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}
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/* Finish transfer. */
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i2c_stop(i2c_smbus, smbus_addr);
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}
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break;
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case 0x03:
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dev->ctl = (dev->ctl & 0x00ff) | (val << 8);
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break;
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case 0x04:
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dev->addr = val;
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break;
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case 0x05:
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dev->cmd = val;
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break;
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case 0x08 ... 0x0f:
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dev->data[dev->index & 0x07] = val;
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break;
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case 0x10:
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dev->saved_addr = val;
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break;
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case 0x11:
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dev->data0 = val;
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break;
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case 0x12:
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dev->data1 = val;
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break;
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case 0x13:
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dev->alias = val & 0xfe;
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break;
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case 0xff:
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dev->reg_ff = val & 0x3f;
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break;
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default:
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break;
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}
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if (dev->next_stat != 0x04) { /* schedule dispatch of any pending status register update */
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dev->stat = 0x08; /* raise HOST_BUSY while waiting */
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timer_disable(&dev->response_timer);
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/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * 60us period measured on real VIA 686B */
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timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * 60 * TIMER_USEC);
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}
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}
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static void
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smbus_sis5595_response(void *priv)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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/* Dispatch the status register update. */
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dev->stat = dev->next_stat;
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}
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static void
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smbus_sis5595_reset(void *priv)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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timer_disable(&dev->response_timer);
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dev->stat = 0x0000;
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dev->block_ptr = 0x01;
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}
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static void *
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smbus_sis5595_init(const device_t *info)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) malloc(sizeof(smbus_sis5595_t));
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memset(dev, 0, sizeof(smbus_sis5595_t));
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dev->local = info->local;
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/* We save the I2C bus handle on dev but use i2c_smbus for all operations because
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dev and therefore dev->i2c will be invalidated if a device triggers a hard reset. */
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i2c_smbus = dev->i2c = i2c_addbus("smbus_sis5595");
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timer_add(&dev->response_timer, smbus_sis5595_response, dev, 0);
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smbus_sis5595_reset(dev);
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return dev;
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}
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static void
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smbus_sis5595_close(void *priv)
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{
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smbus_sis5595_t *dev = (smbus_sis5595_t *) priv;
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if (i2c_smbus == dev->i2c)
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i2c_smbus = NULL;
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i2c_removebus(dev->i2c);
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free(dev);
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}
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const device_t sis5595_smbus_device = {
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.name = "SiS 5595-compatible SMBus Host Controller",
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.internal_name = "sis5595_smbus",
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.flags = DEVICE_AT,
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.local = 0,
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.init = smbus_sis5595_init,
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.close = smbus_sis5595_close,
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.reset = smbus_sis5595_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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