412 lines
10 KiB
C
412 lines
10 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the UMC HB4 "Super Energy Star Green" PCI Chipset.
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*
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* Note: This chipset has no datasheet, everything were done via
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* reverse engineering the BIOS of various machines using it.
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*
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* Note 2: Additional information were also used from all
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* around the web.
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*
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*
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Tiseno100.
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* Copyright 2021 Miran Grca.
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*/
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/*
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UMC HB4 Configuration Registers
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Sources & Notes:
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Cache registers were found at Vogons: https://www.vogons.org/viewtopic.php?f=46&t=68829&start=20
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Basic Reverse engineering effort was done personally by me
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Warning: Register documentation may be inaccurate!
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UMC 8881x:
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Register 50:
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Bit 7: Enable L2 Cache
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Bit 6: Cache Policy (0: Write Thru / 1: Write Back)
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Bit 5-4 Cache Speed
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0 0 Read 3-2-2-2 Write 3T
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0 1 Read 3-1-1-1 Write 3T
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1 0 Read 2-2-2-2 Write 2T
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1 1 Read 2-1-1-1 Write 2T
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Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
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Bit 2-1-0 Cache Size
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0 0 0 0KB
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0 0 1 64KB
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x-x-x Multiplications of 2(64*2 for 0 1 0) till 2MB
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Register 51:
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Bit 7-6 DRAM Read Speed
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5-4 DRAM Write Speed
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0 0 1 Waits
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0 1 1 Waits
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1 0 1 Wait
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1 1 0 Waits
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Bit 3 Resource Lock Enable
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Bit 2 Graphics Adapter (0: VL Bus / 1: PCI Bus)
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Bit 1 L1 WB Policy (0: WT / 1: WB)
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Bit 0 L2 Cache Tag Lenght (0: 7 Bits / 1: 8 Bits)
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Register 52:
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Bit 7: Host-to-PCI Post Write (0: 1 Wait State / 1: 0 Wait States)
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Register 54:
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Bit 7: DC000-DFFFF Read Enable
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Bit 6: D8000-DBFFF Read Enable
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Bit 5: D4000-D7FFF Read Enable
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Bit 4: D0000-D3FFF Read Enable
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Bit 3: CC000-CFFFF Read Enable
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Bit 2: C8000-CBFFF Read Enable
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Bit 1: C0000-C7FFF Read Enable
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Bit 0: Enable C0000-DFFFF Shadow Segment Bits
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Register 55:
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Bit 7: E0000-FFFF Read Enable
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Bit 6: Shadow Write Status (1: Write Protect/0: Write)
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Register 56h & 57h: DRAM Bank 0 Configuration
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Register 58h & 59h: DRAM Bank 1 Configuration
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Register 60:
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Bit 5: If set and SMRAM is enabled, data cycles go to PCI and code cycles go to DRAM
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Bit 0: SMRAM Local Access Enable - if set, SMRAM is also enabled outside SMM
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SMRAM appears to always be enabled in SMM, and always set to A0000-BFFFF.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include "x86.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/smram.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_HB4_LOG
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int hb4_do_log = ENABLE_HB4_LOG;
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static void
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hb4_log(const char *fmt, ...)
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{
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va_list ap;
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if (hb4_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define hb4_log(fmt, ...)
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#endif
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typedef struct hb4_t {
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uint8_t shadow;
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uint8_t shadow_read;
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uint8_t shadow_write;
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uint8_t pci_slot;
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uint8_t pci_conf[256]; /* PCI Registers */
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int mem_state[9];
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smram_t *smram[3]; /* SMRAM Handlers */
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} hb4_t;
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static int shadow_bios[4] = { (MEM_READ_EXTANY | MEM_WRITE_INTERNAL), (MEM_READ_EXTANY | MEM_WRITE_EXTANY),
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(MEM_READ_INTERNAL | MEM_WRITE_INTERNAL), (MEM_READ_INTERNAL | MEM_WRITE_EXTANY) };
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static int shadow_read[2] = { MEM_READ_EXTANY, MEM_READ_INTERNAL };
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static int shadow_write[2] = { MEM_WRITE_INTERNAL, MEM_WRITE_EXTANY };
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int
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hb4_shadow_bios_high(hb4_t *dev)
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{
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int state;
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state = shadow_bios[dev->pci_conf[0x55] >> 6];
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if (state != dev->mem_state[8]) {
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mem_set_mem_state_both(0xf0000, 0x10000, state);
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if ((dev->mem_state[8] & MEM_READ_INTERNAL) && !(state & MEM_READ_INTERNAL))
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mem_invalidate_range(0xf0000, 0xfffff);
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dev->mem_state[8] = state;
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return 1;
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}
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return 0;
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}
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int
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hb4_shadow_bios_low(hb4_t *dev)
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{
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int state;
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state = shadow_bios[(dev->pci_conf[0x55] >> 6) & (dev->shadow | 0x01)];
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if (state != dev->mem_state[7]) {
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mem_set_mem_state_both(0xe0000, 0x10000, state);
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dev->mem_state[7] = state;
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return 1;
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}
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return 0;
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}
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int
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hb4_shadow_main(hb4_t *dev)
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{
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int state;
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int n = 0;
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for (uint8_t i = 0; i < 6; i++) {
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state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> (i + 2)) & 0x01)] | shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
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if (state != dev->mem_state[i + 1]) {
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n++;
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mem_set_mem_state_both(0xc8000 + (i << 14), 0x4000, state);
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dev->mem_state[i + 1] = state;
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}
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}
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return n;
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}
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int
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hb4_shadow_video(hb4_t *dev)
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{
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int state;
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state = shadow_read[dev->shadow && ((dev->pci_conf[0x54] >> 1) & 0x01)] | shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
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if (state != dev->mem_state[0]) {
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mem_set_mem_state_both(0xc0000, 0x8000, state);
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dev->mem_state[0] = state;
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return 1;
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}
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return 0;
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}
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void
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hb4_shadow(hb4_t *dev)
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{
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int n = 0;
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hb4_log("SHADOW: %02X%02X\n", dev->pci_conf[0x55], dev->pci_conf[0x54]);
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n = hb4_shadow_bios_high(dev);
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n += hb4_shadow_bios_low(dev);
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n += hb4_shadow_main(dev);
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n += hb4_shadow_video(dev);
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if (n > 0)
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flushmmucache_nopc();
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}
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static void
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hb4_smram(hb4_t *dev)
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{
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smram_disable_all();
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/* Bit 0, if set, enables SMRAM access outside SMM. SMRAM appears to be always enabled
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in SMM, and is always set to A0000-BFFFF. */
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smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
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/* There's a mirror of the SMRAM at 0E0A0000, mapped to A0000. */
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smram_enable(dev->smram[1], 0x0e0a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
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/* There's another mirror of the SMRAM at 4E0A0000, mapped to A0000. */
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smram_enable(dev->smram[2], 0x4e0a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
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/* Bit 5 seems to set data to go to PCI and code to DRAM. The Samsung SPC7700P-LW uses
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this. */
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if (dev->pci_conf[0x60] & 0x20) {
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if (dev->pci_conf[0x60] & 0x01)
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mem_set_mem_state_smram_ex(0, 0x000a0000, 0x20000, 0x02);
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mem_set_mem_state_smram_ex(1, 0x000a0000, 0x20000, 0x02);
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}
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}
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static void
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hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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{
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hb4_t *dev = (hb4_t *) priv;
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hb4_log("UM8881: dev->regs[%02x] = %02x POST: %02x \n", addr, val, inb(0x80));
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switch (addr) {
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case 0x04:
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case 0x05:
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dev->pci_conf[addr] = val;
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break;
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case 0x07:
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dev->pci_conf[addr] &= ~(val & 0xf9);
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break;
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case 0x0c:
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case 0x0d:
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dev->pci_conf[addr] = val;
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break;
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case 0x50:
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dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
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cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/
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cpu_update_waitstates();
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break;
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case 0x51:
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case 0x52:
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dev->pci_conf[addr] = val;
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break;
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case 0x53:
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dev->pci_conf[addr] = val;
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hb4_log("HB53: %02X\n", val);
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break;
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case 0x55:
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dev->shadow_read = (val & 0x80);
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dev->shadow_write = (val & 0x40);
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dev->pci_conf[addr] = val;
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hb4_shadow(dev);
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break;
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case 0x54:
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dev->shadow = (val & 0x01) << 1;
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dev->pci_conf[addr] = val;
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hb4_shadow(dev);
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break;
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case 0x56 ... 0x5f:
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dev->pci_conf[addr] = val;
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break;
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case 0x60:
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dev->pci_conf[addr] = val;
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hb4_smram(dev);
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break;
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case 0x61:
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dev->pci_conf[addr] = val;
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break;
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default:
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break;
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}
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}
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static uint8_t
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hb4_read(int func, int addr, void *priv)
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{
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const hb4_t *dev = (hb4_t *) priv;
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uint8_t ret = 0xff;
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if (func == 0)
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ret = dev->pci_conf[addr];
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return ret;
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}
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static void
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hb4_reset(void *priv)
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{
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hb4_t *dev = (hb4_t *) priv;
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memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
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dev->pci_conf[0] = 0x60; /* UMC */
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dev->pci_conf[1] = 0x10;
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dev->pci_conf[2] = 0x81; /* 8881x */
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dev->pci_conf[3] = 0x88;
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dev->pci_conf[7] = 2;
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dev->pci_conf[8] = 4;
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dev->pci_conf[0x09] = 0x00;
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dev->pci_conf[0x0a] = 0x00;
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dev->pci_conf[0x0b] = 0x06;
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dev->pci_conf[0x51] = 1;
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dev->pci_conf[0x52] = 1;
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dev->pci_conf[0x5a] = 4;
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dev->pci_conf[0x5c] = 0xc0;
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dev->pci_conf[0x5d] = 0x20;
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dev->pci_conf[0x5f] = 0xff;
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hb4_write(0, 0x54, 0x00, dev);
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hb4_write(0, 0x55, 0x00, dev);
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hb4_write(0, 0x60, 0x80, dev);
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cpu_cache_ext_enabled = 0;
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cpu_update_waitstates();
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memset(dev->mem_state, 0x00, sizeof(dev->mem_state));
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}
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static void
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hb4_close(void *priv)
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{
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hb4_t *dev = (hb4_t *) priv;
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free(dev);
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}
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static void *
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hb4_init(UNUSED(const device_t *info))
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{
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hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
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memset(dev, 0, sizeof(hb4_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev, &dev->pci_slot); /* Device 10: UMC 8881x */
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/* Port 92 */
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device_add(&port_92_pci_device);
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/* SMRAM */
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dev->smram[0] = smram_add();
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dev->smram[1] = smram_add();
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dev->smram[2] = smram_add();
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hb4_reset(dev);
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return dev;
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}
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const device_t umc_hb4_device = {
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.name = "UMC HB4(8881F)",
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.internal_name = "umc_hb4",
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.flags = DEVICE_PCI,
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.local = 0x886a,
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.init = hb4_init,
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.close = hb4_close,
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.reset = hb4_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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