752 lines
26 KiB
C
752 lines
26 KiB
C
#include <stdint.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/mem.h>
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#include <86box/plat_unused.h>
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#include "x86_ops.h"
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#include "codegen.h"
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#include "x86.h"
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#include "x86seg_common.h"
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#include "x86seg.h"
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#include "386_common.h"
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#include "codegen_accumulate.h"
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#include "codegen_allocator.h"
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#include "codegen_backend.h"
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#include "codegen_ir.h"
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#include "codegen_ops.h"
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#include "codegen_ops_helpers.h"
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#define MAX_INSTRUCTION_COUNT 50
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static struct {
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uint32_t pc;
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int op_ssegs;
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x86seg *op_ea_seg;
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uint32_t op_32;
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int first_uop;
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int TOP;
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} codegen_instructions[MAX_INSTRUCTION_COUNT];
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int
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codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction, int *TOP)
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{
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for (uint8_t c = 0; c <= block->ins; c++) {
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if (codegen_instructions[c].pc == pc) {
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*first_instruction = c;
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*TOP = codegen_instructions[c].TOP;
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return codegen_instructions[c].first_uop;
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}
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}
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*first_instruction = block->ins;
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return -1;
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}
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void
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codegen_set_loop_start(ir_data_t *ir, int first_instruction)
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{
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uop_MOV_IMM(ir, IREG_op32, codegen_instructions[first_instruction].op_32);
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uop_MOV_PTR(ir, IREG_ea_seg, (void *) codegen_instructions[first_instruction].op_ea_seg);
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uop_MOV_IMM(ir, IREG_ssegs, codegen_instructions[first_instruction].op_ssegs);
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}
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int has_ea;
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codeblock_t *codeblock;
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uint16_t *codeblock_hash;
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void (*codegen_timing_start)(void);
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void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
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void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
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void (*codegen_timing_block_start)(void);
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void (*codegen_timing_block_end)(void);
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int (*codegen_timing_jump_cycles)(void);
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void
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codegen_timing_set(codegen_timing_t *timing)
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{
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codegen_timing_start = timing->start;
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codegen_timing_prefix = timing->prefix;
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codegen_timing_opcode = timing->opcode;
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codegen_timing_block_start = timing->block_start;
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codegen_timing_block_end = timing->block_end;
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codegen_timing_jump_cycles = timing->jump_cycles;
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}
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int codegen_in_recompile;
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static int last_op_ssegs;
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static x86seg *last_op_ea_seg;
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static uint32_t last_op_32;
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void
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codegen_generate_reset(void)
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{
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last_op_ssegs = -1;
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last_op_ea_seg = NULL;
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last_op_32 = -1;
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has_ea = 0;
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}
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void
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codegen_check_seg_read(UNUSED(codeblock_t *block), ir_data_t *ir, x86seg *seg)
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{
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/*Segments always valid in real/V86 mode*/
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if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
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return;
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/*CS and SS must always be valid*/
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if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
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return;
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if (seg->checked)
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return;
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if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
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return;
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uop_CMP_IMM_JZ(ir, ireg_seg_base(seg), (uint32_t) -1, codegen_gpf_rout);
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seg->checked = 1;
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}
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void
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codegen_check_seg_write(UNUSED(codeblock_t *block), ir_data_t *ir, x86seg *seg)
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{
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/*Segments always valid in real/V86 mode*/
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if (!(cr0 & 1) || (cpu_state.eflags & VM_FLAG))
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return;
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/*CS and SS must always be valid*/
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if (seg == &cpu_state.seg_cs || seg == &cpu_state.seg_ss)
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return;
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if (seg->checked)
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return;
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if (seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS))
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return;
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uop_CMP_IMM_JZ(ir, ireg_seg_base(seg), (uint32_t) -1, codegen_gpf_rout);
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seg->checked = 1;
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}
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static x86seg *
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codegen_generate_ea_16_long(ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc)
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{
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uint32_t old_pc = (*op_pc) + 1;
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if (!cpu_mod && cpu_rm == 6) {
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uint16_t addr = (fetchdat >> 8) & 0xffff;
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uop_MOV_IMM(ir, IREG_eaaddr, addr);
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(*op_pc) += 2;
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} else {
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int base_reg;
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int index_reg;
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int offset;
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switch (cpu_rm & 7) {
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default:
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case 0:
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case 1:
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case 7:
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base_reg = IREG_EBX;
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break;
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case 2:
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case 3:
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case 6:
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base_reg = IREG_EBP;
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break;
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case 4:
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base_reg = IREG_ESI;
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break;
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case 5:
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base_reg = IREG_EDI;
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break;
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}
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uop_MOV(ir, IREG_eaaddr, base_reg);
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if (!(cpu_rm & 4)) {
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if (!(cpu_rm & 1))
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index_reg = IREG_ESI;
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else
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index_reg = IREG_EDI;
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, index_reg);
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}
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switch (cpu_mod) {
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case 1:
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offset = (int) (int8_t) ((fetchdat >> 8) & 0xff);
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, offset);
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(*op_pc)++;
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break;
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case 2:
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offset = (fetchdat >> 8) & 0xffff;
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, offset);
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(*op_pc) += 2;
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break;
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default:
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break;
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}
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uop_AND_IMM(ir, IREG_eaaddr, IREG_eaaddr, 0xffff);
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if (mod1seg[cpu_rm] == &ss && !op_ssegs) {
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op_ea_seg = &cpu_state.seg_ss;
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}
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}
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codegen_mark_code_present(ir->block, cs + old_pc, ((*op_pc) + 1) - old_pc);
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return op_ea_seg;
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}
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static x86seg *
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codegen_generate_ea_32_long(ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, int stack_offset)
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{
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codeblock_t *block = ir->block;
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uint32_t old_pc = (*op_pc) + 1;
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uint32_t new_eaaddr;
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int extra_bytes = 0;
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if (cpu_rm == 4) {
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uint8_t sib = fetchdat >> 8;
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(*op_pc)++;
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switch (cpu_mod) {
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case 0:
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if ((sib & 7) == 5) {
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if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
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LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_eaaddr, cs + (*op_pc) + 1);
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extra_bytes = 1;
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} else {
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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extra_bytes = 5;
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}
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(*op_pc) += 4;
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} else {
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uop_MOV(ir, IREG_eaaddr, sib & 7);
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extra_bytes = 1;
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}
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break;
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case 1:
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new_eaaddr = (uint32_t) (int8_t) ((fetchdat >> 16) & 0xff);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, sib & 7);
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(*op_pc)++;
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extra_bytes = 2;
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break;
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case 2:
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if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
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LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_eaaddr, cs + (*op_pc) + 1);
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extra_bytes = 1;
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} else {
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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extra_bytes = 5;
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}
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(*op_pc) += 4;
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, sib & 7);
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break;
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default:
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break;
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}
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if (stack_offset && (sib & 7) == 4 && (cpu_mod || (sib & 7) != 5)) { /*ESP*/
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, stack_offset);
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#if 0
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addbyte(0x05);
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addlong(stack_offset);
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#endif
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}
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if (((sib & 7) == 4 || (cpu_mod && (sib & 7) == 5)) && !op_ssegs)
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op_ea_seg = &cpu_state.seg_ss;
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if (((sib >> 3) & 7) != 4) {
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switch (sib >> 6) {
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case 0:
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7);
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break;
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case 1:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 1);
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break;
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case 2:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 2);
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break;
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case 3:
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uop_ADD_LSHIFT(ir, IREG_eaaddr, IREG_eaaddr, (sib >> 3) & 7, 3);
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break;
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default:
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break;
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}
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}
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} else {
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if (!cpu_mod && cpu_rm == 5) {
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if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
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LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_eaaddr, cs + (*op_pc) + 1);
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} else {
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_MOV_IMM(ir, IREG_eaaddr, new_eaaddr);
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extra_bytes = 4;
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}
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(*op_pc) += 4;
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} else {
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uop_MOV(ir, IREG_eaaddr, cpu_rm);
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if (cpu_mod) {
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if (cpu_rm == 5 && !op_ssegs)
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op_ea_seg = &cpu_state.seg_ss;
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if (cpu_mod == 1) {
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, (uint32_t) (int8_t) (fetchdat >> 8));
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(*op_pc)++;
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extra_bytes = 1;
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} else {
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if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
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LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + (*op_pc) + 1);
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uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, IREG_temp0);
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} else {
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new_eaaddr = fastreadl(cs + (*op_pc) + 1);
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uop_ADD_IMM(ir, IREG_eaaddr, IREG_eaaddr, new_eaaddr);
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extra_bytes = 4;
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}
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(*op_pc) += 4;
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}
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}
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}
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}
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if (extra_bytes)
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codegen_mark_code_present(ir->block, cs + old_pc, extra_bytes);
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return op_ea_seg;
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}
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x86seg *
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codegen_generate_ea(ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, uint32_t op_32, int stack_offset)
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{
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cpu_mod = (fetchdat >> 6) & 3;
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cpu_reg = (fetchdat >> 3) & 7;
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cpu_rm = fetchdat & 7;
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if ((fetchdat & 0xc0) == 0xc0)
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return NULL;
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if (op_32 & 0x200)
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return codegen_generate_ea_32_long(ir, op_ea_seg, fetchdat, op_ssegs, op_pc, stack_offset);
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return codegen_generate_ea_16_long(ir, op_ea_seg, fetchdat, op_ssegs, op_pc);
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}
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// clang-format off
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static uint8_t opcode_modrm[256] = {
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*10*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*20*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*30*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
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0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, /*60*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*70*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*80*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
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1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
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1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*d0*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
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0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, /*f0*/
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};
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static uint8_t opcode_0f_modrm[256] = {
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, /*00*/
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, /*10*/
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1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*30*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*40*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, /*60*/
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0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, /*70*/
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
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0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
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1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
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1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
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0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*d0*/
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0, 1, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 0, 1, /*e0*/
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0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0 /*f0*/
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};
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// clang-format on
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void
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codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc)
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{
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codeblock_t *block = &codeblock[block_current];
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ir_data_t *ir = codegen_get_ir_data();
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uint32_t op_pc = new_pc;
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const OpFn *op_table = x86_dynarec_opcodes;
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RecompOpFn *recomp_op_table = recomp_opcodes;
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int opcode_shift = 0;
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int opcode_mask = 0x3ff;
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uint32_t recomp_opcode_mask = 0x1ff;
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uint32_t op_32 = use32;
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int over = 0;
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int test_modrm = 1;
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int pc_off = 0;
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uint32_t next_pc = 0;
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#ifdef DEBUG_EXTRA
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uint8_t last_prefix = 0;
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#endif
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op_ea_seg = &cpu_state.seg_ds;
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op_ssegs = 0;
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codegen_timing_start();
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while (!over) {
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switch (opcode) {
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case 0x0f:
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#ifdef DEBUG_EXTRA
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last_prefix = 0x0f;
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#endif
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op_table = x86_dynarec_opcodes_0f;
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recomp_op_table = fpu_softfloat ? recomp_opcodes_0f_no_mmx : recomp_opcodes_0f;
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over = 1;
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break;
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case 0x26: /*ES:*/
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op_ea_seg = &cpu_state.seg_es;
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op_ssegs = 1;
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break;
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case 0x2e: /*CS:*/
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op_ea_seg = &cpu_state.seg_cs;
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op_ssegs = 1;
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break;
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case 0x36: /*SS:*/
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op_ea_seg = &cpu_state.seg_ss;
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op_ssegs = 1;
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break;
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case 0x3e: /*DS:*/
|
|
op_ea_seg = &cpu_state.seg_ds;
|
|
op_ssegs = 1;
|
|
break;
|
|
case 0x64: /*FS:*/
|
|
op_ea_seg = &cpu_state.seg_fs;
|
|
op_ssegs = 1;
|
|
break;
|
|
case 0x65: /*GS:*/
|
|
op_ea_seg = &cpu_state.seg_gs;
|
|
op_ssegs = 1;
|
|
break;
|
|
|
|
case 0x66: /*Data size select*/
|
|
op_32 = ((use32 & 0x100) ^ 0x100) | (op_32 & 0x200);
|
|
break;
|
|
case 0x67: /*Address size select*/
|
|
op_32 = ((use32 & 0x200) ^ 0x200) | (op_32 & 0x100);
|
|
break;
|
|
|
|
case 0xd8:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xd8;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d8;
|
|
opcode_shift = 3;
|
|
opcode_mask = 0x1f;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xd9:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xd9;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d9_a32 : x86_dynarec_opcodes_d9_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d9;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xda:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xda;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_da_a32 : x86_dynarec_opcodes_da_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_da;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xdb:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xdb;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_db_a32 : x86_dynarec_opcodes_db_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_db;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xdc:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xdc;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dc_a32 : x86_dynarec_opcodes_dc_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dc;
|
|
opcode_shift = 3;
|
|
opcode_mask = 0x1f;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xdd:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xdd;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dd_a32 : x86_dynarec_opcodes_dd_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dd;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xde:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xde;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_de_a32 : x86_dynarec_opcodes_de_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_de;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
case 0xdf:
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xdf;
|
|
#endif
|
|
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_df_a32 : x86_dynarec_opcodes_df_a16;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_df;
|
|
opcode_mask = 0xff;
|
|
over = 1;
|
|
pc_off = -1;
|
|
test_modrm = 0;
|
|
block->flags |= CODEBLOCK_HAS_FPU;
|
|
break;
|
|
|
|
case 0xf0: /*LOCK*/
|
|
break;
|
|
|
|
case 0xf2: /*REPNE*/
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xf2;
|
|
#endif
|
|
op_table = x86_dynarec_opcodes_REPNE;
|
|
recomp_op_table = NULL; // recomp_opcodes_REPNE;
|
|
break;
|
|
case 0xf3: /*REPE*/
|
|
#ifdef DEBUG_EXTRA
|
|
last_prefix = 0xf3;
|
|
#endif
|
|
op_table = x86_dynarec_opcodes_REPE;
|
|
recomp_op_table = NULL; // recomp_opcodes_REPE;
|
|
break;
|
|
|
|
default:
|
|
goto generate_call;
|
|
}
|
|
fetchdat = fastreadl(cs + op_pc);
|
|
codegen_timing_prefix(opcode, fetchdat);
|
|
if (cpu_state.abrt)
|
|
return;
|
|
opcode = fetchdat & 0xff;
|
|
if (!pc_off)
|
|
fetchdat >>= 8;
|
|
|
|
op_pc++;
|
|
}
|
|
|
|
generate_call:
|
|
codegen_instructions[block->ins].pc = cpu_state.oldpc;
|
|
codegen_instructions[block->ins].op_ssegs = last_op_ssegs;
|
|
codegen_instructions[block->ins].op_ea_seg = last_op_ea_seg;
|
|
codegen_instructions[block->ins].op_32 = last_op_32;
|
|
codegen_instructions[block->ins].TOP = cpu_state.TOP;
|
|
codegen_instructions[block->ins].first_uop = ir->wr_pos;
|
|
|
|
codegen_timing_opcode(opcode, fetchdat, op_32, op_pc);
|
|
|
|
codegen_accumulate(ir, ACCREG_cycles, -codegen_block_cycles);
|
|
codegen_block_cycles = 0;
|
|
|
|
if ((op_table == x86_dynarec_opcodes && ((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 || (opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 || (opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) || (op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80))) {
|
|
/*On some CPUs (eg K6), a jump/branch instruction may be able to pair with
|
|
subsequent instructions, so no cycles may have been deducted for it yet.
|
|
To prevent having zero cycle blocks (eg with a jump instruction pointing
|
|
to itself), apply the cycles that would be taken if this jump is taken,
|
|
then reverse it for subsequent instructions if the jump is not taken*/
|
|
int jump_cycles = 0;
|
|
|
|
if (codegen_timing_jump_cycles)
|
|
codegen_timing_jump_cycles();
|
|
|
|
if (jump_cycles)
|
|
codegen_accumulate(ir, ACCREG_cycles, -jump_cycles);
|
|
codegen_accumulate_flush(ir);
|
|
if (jump_cycles)
|
|
codegen_accumulate(ir, ACCREG_cycles, jump_cycles);
|
|
}
|
|
|
|
if (op_table == x86_dynarec_opcodes_0f && opcode == 0x0f) {
|
|
/*3DNow opcodes are stored after ModR/M, SIB and any offset*/
|
|
uint8_t modrm = fetchdat & 0xff;
|
|
uint8_t sib = (fetchdat >> 8) & 0xff;
|
|
uint32_t opcode_pc = op_pc + 1;
|
|
uint8_t opcode_3dnow;
|
|
|
|
if ((modrm & 0xc0) != 0xc0) {
|
|
if (op_32 & 0x200) {
|
|
if ((modrm & 7) == 4) {
|
|
/* Has SIB*/
|
|
opcode_pc++;
|
|
if ((modrm & 0xc0) == 0x40)
|
|
opcode_pc++;
|
|
else if ((modrm & 0xc0) == 0x80)
|
|
opcode_pc += 4;
|
|
else if ((sib & 0x07) == 0x05)
|
|
opcode_pc += 4;
|
|
} else {
|
|
if ((modrm & 0xc0) == 0x40)
|
|
opcode_pc++;
|
|
else if ((modrm & 0xc0) == 0x80)
|
|
opcode_pc += 4;
|
|
else if ((modrm & 0xc7) == 0x05)
|
|
opcode_pc += 4;
|
|
}
|
|
} else {
|
|
if ((modrm & 0xc0) == 0x40)
|
|
opcode_pc++;
|
|
else if ((modrm & 0xc0) == 0x80)
|
|
opcode_pc += 2;
|
|
else if ((modrm & 0xc7) == 0x06)
|
|
opcode_pc += 2;
|
|
}
|
|
}
|
|
|
|
opcode_3dnow = fastreadb(cs + opcode_pc);
|
|
if (!fpu_softfloat && recomp_opcodes_3DNOW[opcode_3dnow]) {
|
|
next_pc = opcode_pc + 1;
|
|
|
|
op_table = x86_dynarec_opcodes_3DNOW;
|
|
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_3DNOW;
|
|
opcode = opcode_3dnow;
|
|
recomp_opcode_mask = 0xff;
|
|
opcode_mask = 0xff;
|
|
}
|
|
}
|
|
codegen_mark_code_present(block, cs + old_pc, (op_pc - old_pc) - pc_off);
|
|
/* It is apparently a prefixed instruction. */
|
|
#if 0
|
|
if ((recomp_op_table == recomp_opcodes) && (opcode == 0x48))
|
|
goto codegen_skip;
|
|
#endif
|
|
|
|
if (recomp_op_table && recomp_op_table[(opcode | op_32) & recomp_opcode_mask]) {
|
|
uint32_t new_pc = recomp_op_table[(opcode | op_32) & recomp_opcode_mask](block, ir, opcode, fetchdat, op_32, op_pc);
|
|
if (new_pc) {
|
|
if (new_pc != -1)
|
|
uop_MOV_IMM(ir, IREG_pc, new_pc);
|
|
|
|
codegen_endpc = (cs + cpu_state.pc) + 8;
|
|
|
|
block->ins++;
|
|
|
|
if (block->ins >= MAX_INSTRUCTION_COUNT)
|
|
CPU_BLOCK_END();
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
// codegen_skip:
|
|
if ((op_table == x86_dynarec_opcodes_REPNE || op_table == x86_dynarec_opcodes_REPE) && !op_table[opcode | op_32]) {
|
|
op_table = x86_dynarec_opcodes;
|
|
recomp_op_table = recomp_opcodes;
|
|
}
|
|
|
|
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
|
|
|
|
if (!test_modrm || (op_table == x86_dynarec_opcodes && opcode_modrm[opcode]) || (op_table == x86_dynarec_opcodes_0f && opcode_0f_modrm[opcode]) || (op_table == x86_dynarec_opcodes_3DNOW)) {
|
|
int stack_offset = 0;
|
|
|
|
if (op_table == x86_dynarec_opcodes && opcode == 0x8f) /*POP*/
|
|
stack_offset = (op_32 & 0x100) ? 4 : 2;
|
|
|
|
cpu_mod = (fetchdat >> 6) & 3;
|
|
cpu_reg = (fetchdat >> 3) & 7;
|
|
cpu_rm = fetchdat & 7;
|
|
|
|
uop_MOV_IMM(ir, IREG_rm_mod_reg, cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
|
|
|
|
op_pc += pc_off;
|
|
if (cpu_mod != 3 && !(op_32 & 0x200)) {
|
|
op_ea_seg = codegen_generate_ea_16_long(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc);
|
|
}
|
|
if (cpu_mod != 3 && (op_32 & 0x200)) {
|
|
op_ea_seg = codegen_generate_ea_32_long(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, stack_offset);
|
|
}
|
|
op_pc -= pc_off;
|
|
}
|
|
|
|
#ifdef DEBUG_EXTRA
|
|
uop_LOG_INSTR(ir, opcode | (last_prefix << 8));
|
|
#endif
|
|
codegen_accumulate_flush(ir);
|
|
if (op_table == x86_dynarec_opcodes_3DNOW)
|
|
uop_MOV_IMM(ir, IREG_pc, next_pc);
|
|
else
|
|
uop_MOV_IMM(ir, IREG_pc, op_pc + pc_off);
|
|
uop_MOV_IMM(ir, IREG_oldpc, old_pc);
|
|
if (op_32 != last_op_32)
|
|
uop_MOV_IMM(ir, IREG_op32, op_32);
|
|
if (op_ea_seg != last_op_ea_seg)
|
|
uop_MOV_PTR(ir, IREG_ea_seg, (void *) op_ea_seg);
|
|
if (op_ssegs != last_op_ssegs)
|
|
uop_MOV_IMM(ir, IREG_ssegs, op_ssegs);
|
|
uop_LOAD_FUNC_ARG_IMM(ir, 0, fetchdat);
|
|
uop_CALL_INSTRUCTION_FUNC(ir, op);
|
|
codegen_flags_changed = 0;
|
|
codegen_mark_code_present(block, cs + cpu_state.pc, 8);
|
|
|
|
last_op_32 = op_32;
|
|
last_op_ea_seg = op_ea_seg;
|
|
last_op_ssegs = op_ssegs;
|
|
#if 0
|
|
codegen_block_ins++;
|
|
#endif
|
|
|
|
block->ins++;
|
|
|
|
if (block->ins >= MAX_INSTRUCTION_COUNT)
|
|
CPU_BLOCK_END();
|
|
|
|
codegen_endpc = (cs + cpu_state.pc) + 8;
|
|
|
|
#if 0
|
|
if (has_ea)
|
|
fatal("Has EA\n");
|
|
#endif
|
|
}
|