552 lines
14 KiB
C
552 lines
14 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Western Digital WD76C10 chipset.
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*
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* Note: This chipset has no datasheet, everything were done via
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* reverse engineering the BIOS of various machines using it.
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*
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* Authors: Tiseno100
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*
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* Copyright 2021 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/dma.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/hdd.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/lpt.h>
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#include <86box/mem.h>
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#include <86box/port_92.h>
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#include <86box/serial.h>
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#include <86box/chipset.h>
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/* Lock/Unlock Procedures */
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#define LOCK dev->lock
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#define UNLOCKED !dev->lock
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#define ENABLE_WD76C10_LOG 1
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#ifdef ENABLE_WD76C10_LOG
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int wd76c10_do_log = ENABLE_WD76C10_LOG;
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static void
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wd76c10_log(const char *fmt, ...)
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{
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va_list ap;
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if (wd76c10_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define wd76c10_log(fmt, ...)
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#endif
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typedef struct
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{
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uint16_t lock_reg, oscillator_40mhz, cache_flush, ems_page_reg,
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ems_page_reg_pointer, port_shadow, pmc_interrupt,
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high_mem_protect_boundry, delay_line, diagnostic,
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nmi_status, pmc_input, pmc_timer,
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pmc_output, ems_control_low_address_boundry, shadow_ram,
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split_addr, bank32staddr, bank10staddr,
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non_page_mode_dram_timing, mem_control,
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refresh_control, disk_chip_select, prog_chip_sel_addr,
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bus_timing_power_down_ctl, clk_control;
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int lock;
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fdc_t *fdc_controller;
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mem_mapping_t *mem_mapping;
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serial_t *uart[2];
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} wd76c10_t;
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static void wd76c10_refresh_control(wd76c10_t *dev)
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{
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serial_remove(dev->uart[1]);
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/* Serial B */
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switch ((dev->refresh_control >> 1) & 7)
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{
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case 1:
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serial_setup(dev->uart[1], 0x3f8, 3);
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break;
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case 2:
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serial_setup(dev->uart[1], 0x2f8, 3);
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break;
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case 3:
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serial_setup(dev->uart[1], 0x3e8, 3);
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break;
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case 4:
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serial_setup(dev->uart[1], 0x2e8, 3);
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break;
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}
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serial_remove(dev->uart[0]);
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/* Serial A */
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switch ((dev->refresh_control >> 5) & 7)
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{
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case 1:
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serial_setup(dev->uart[0], 0x3f8, 4);
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break;
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case 2:
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serial_setup(dev->uart[0], 0x2f8, 4);
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break;
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case 3:
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serial_setup(dev->uart[0], 0x3e8, 4);
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break;
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case 4:
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serial_setup(dev->uart[0], 0x2e8, 4);
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break;
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}
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lpt1_remove();
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/* LPT */
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switch ((dev->refresh_control >> 9) & 3)
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{
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case 1:
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lpt1_init(0x3bc);
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lpt1_irq(7);
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break;
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case 2:
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lpt1_init(0x378);
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lpt1_irq(7);
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break;
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case 3:
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lpt1_init(0x278);
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lpt1_irq(7);
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break;
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}
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}
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static void wd76c10_split_addr(wd76c10_t *dev)
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{
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switch ((dev->split_addr >> 8) & 3)
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{
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case 1:
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if (((dev->shadow_ram >> 8) & 3) == 2)
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mem_remap_top(256);
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break;
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case 2:
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if (((dev->shadow_ram >> 8) & 3) == 1)
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mem_remap_top(320);
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break;
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case 3:
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if (((dev->shadow_ram >> 8) & 3) == 3)
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mem_remap_top(384);
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break;
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}
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}
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static void wd76c10_disk_chip_select(wd76c10_t *dev)
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{
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ide_pri_disable();
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if (!(dev->disk_chip_select & 1))
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{
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ide_set_base(0, !(dev->disk_chip_select & 0x0010) ? 0x1f0 : 0x170);
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ide_set_side(0, !(dev->disk_chip_select & 0x0010) ? 0x3f6 : 0x376);
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}
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ide_pri_enable();
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fdc_remove(dev->fdc_controller);
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if (!(dev->disk_chip_select & 2))
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fdc_set_base(dev->fdc_controller, !(dev->disk_chip_select & 0x0010) ? 0x3f0 : 0x370);
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}
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static void wd76c10_shadow_recalc(wd76c10_t *dev)
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{
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switch ((dev->shadow_ram >> 14) & 3)
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{
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case 0:
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mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 1:
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mem_set_mem_state_both(0x80000, 0x20000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
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break;
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case 2:
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mem_set_mem_state_both(0x40000, 0x60000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
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break;
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case 3:
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mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
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break;
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}
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switch ((dev->shadow_ram >> 8) & 3)
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{
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case 0:
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mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
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break;
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case 2:
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mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_INTERNAL | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
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break;
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case 3:
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mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
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break;
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}
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}
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static void
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wd76c10_write(uint16_t addr, uint16_t val, void *priv)
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{
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wd76c10_t *dev = (wd76c10_t *)priv;
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if (UNLOCKED)
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{
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switch (addr)
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{
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case 0x1072:
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dev->clk_control = val;
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break;
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case 0x1872:
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dev->bus_timing_power_down_ctl = val;
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break;
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case 0x2072:
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dev->refresh_control = val;
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wd76c10_refresh_control(dev);
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break;
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case 0x2872:
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dev->disk_chip_select = val;
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wd76c10_disk_chip_select(dev);
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break;
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case 0x3072:
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dev->prog_chip_sel_addr = val;
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break;
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case 0x3872:
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dev->non_page_mode_dram_timing = val;
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break;
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case 0x4072:
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dev->mem_control = val;
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break;
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case 0x4872:
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dev->bank10staddr = val;
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break;
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case 0x5072:
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dev->bank32staddr = val;
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break;
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case 0x5872:
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dev->split_addr = val;
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wd76c10_split_addr(dev);
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break;
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case 0x6072:
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dev->shadow_ram = val & 0xffbf;
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wd76c10_shadow_recalc(dev);
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break;
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case 0x6872:
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dev->ems_control_low_address_boundry = val & 0xecff;
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break;
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case 0x7072:
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dev->pmc_output = (val >> 8) & 0x00ff;
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break;
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case 0x7872:
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dev->pmc_output = val & 0xff00;
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break;
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case 0x8072:
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dev->pmc_timer = val;
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break;
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case 0x8872:
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dev->pmc_input = val;
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break;
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case 0x9072:
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dev->nmi_status = val & 0x00fc;
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break;
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case 0x9872:
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dev->diagnostic = val & 0xfdff;
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break;
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case 0xa072:
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dev->delay_line = val;
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break;
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case 0xc872:
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dev->pmc_interrupt = val & 0xfcfc;
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break;
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case 0xf072:
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dev->oscillator_40mhz = 0;
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break;
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case 0xf472:
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dev->oscillator_40mhz = 1;
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break;
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case 0xf872:
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dev->cache_flush = val;
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flushmmucache();
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break;
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}
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wd76c10_log("WD76C10: dev->regs[%04x] = %04x\n", addr, val);
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}
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switch (addr)
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{
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case 0xe072:
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dev->ems_page_reg_pointer = val & 0x003f;
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break;
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case 0xe872:
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dev->ems_page_reg = val & 0x8fff;
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break;
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case 0xf073:
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dev->lock_reg = val & 0x00ff;
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LOCK = !(val & 0x00da);
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break;
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}
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}
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static uint16_t
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wd76c10_read(uint16_t addr, void *priv)
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{
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wd76c10_t *dev = (wd76c10_t *)priv;
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wd76c10_log("WD76C10: R dev->regs[%04x]\n", addr);
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switch (addr)
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{
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case 0x1072:
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return dev->clk_control;
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case 0x1872:
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return dev->bus_timing_power_down_ctl;
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case 0x2072:
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return dev->refresh_control;
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case 0x2872:
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return dev->disk_chip_select;
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case 0x3072:
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return dev->prog_chip_sel_addr;
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case 0x3872:
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return dev->non_page_mode_dram_timing;
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case 0x4072:
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return dev->mem_control;
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case 0x4872:
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return dev->bank10staddr;
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case 0x5072:
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return dev->bank32staddr;
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case 0x5872:
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return dev->split_addr;
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case 0x6072:
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return dev->shadow_ram;
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case 0x6872:
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return dev->ems_control_low_address_boundry;
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case 0x7072:
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return (dev->pmc_output << 8) & 0xff00;
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case 0x7872:
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return (dev->pmc_output) & 0xff00;
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case 0x8072:
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return dev->pmc_timer;
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case 0x8872:
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return dev->pmc_input;
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case 0x9072:
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return dev->nmi_status;
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case 0x9872:
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return dev->diagnostic;
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case 0xa072:
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return dev->delay_line;
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case 0xb872:
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return (inb(0x040b) << 8) | inb(0x04d6);
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case 0xc872:
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return dev->pmc_interrupt;
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case 0xd072:
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return dev->port_shadow;
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case 0xe072:
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return dev->ems_page_reg_pointer;
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case 0xe872:
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return dev->ems_page_reg;
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case 0xfc72:
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return 0x0ff0;
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default:
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return 0xffff;
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}
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}
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static void
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wd76c10_close(void *priv)
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{
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wd76c10_t *dev = (wd76c10_t *)priv;
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free(dev);
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}
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static void *
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wd76c10_init(const device_t *info)
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{
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wd76c10_t *dev = (wd76c10_t *)malloc(sizeof(wd76c10_t));
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memset(dev, 0, sizeof(wd76c10_t));
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device_add(&port_92_inv_device);
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dev->uart[0] = device_add_inst(&ns16450_device, 1);
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dev->uart[1] = device_add_inst(&ns16450_device, 2);
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dev->fdc_controller = device_add(&fdc_at_device);
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device_add(&ide_isa_device);
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/* Lock Configuration */
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LOCK = 1;
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/* Clock Control */
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io_sethandler(0x1072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Bus Timing & Power Down Control */
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io_sethandler(0x1872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Refresh Control(Serial & Parallel) */
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io_sethandler(0x2072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Disk Chip Select */
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io_sethandler(0x2872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Programmable Chip Select Address(Needs more further examination!) */
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io_sethandler(0x3072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Bank 1 & 0 Start Address */
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io_sethandler(0x4872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Bank 3 & 2 Start Address */
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io_sethandler(0x5072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Split Address */
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io_sethandler(0x5872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* EMS Control & EMS Low level boundry */
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io_sethandler(0x6072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* EMS Control & EMS Low level boundry */
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io_sethandler(0x6872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* PMC Output */
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io_sethandler(0x7072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* PMC Output */
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io_sethandler(0x7872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* PMC Status */
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io_sethandler(0x8072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* PMC Status */
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io_sethandler(0x8872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* NMI Status (Needs further checkup) */
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io_sethandler(0x9072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Diagnostics */
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io_sethandler(0x9872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Delay Line */
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io_sethandler(0xa072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* DMA Mode Shadow(Needs Involvement on the DMA code) */
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io_sethandler(0xb872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
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/* High Memory Protection Boundry */
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io_sethandler(0xc072, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
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/* PMC Interrupt Enable */
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io_sethandler(0xc872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
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/* Port Shadow (Needs further lookup) */
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io_sethandler(0xd072, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
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/* EMS Page Register Pointer */
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io_sethandler(0xe072, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* EMS Page Register */
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io_sethandler(0xe872, 1, NULL, wd76c10_read, NULL, NULL, wd76c10_write, NULL, dev);
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/* Lock/Unlock Configuration */
|
|
io_sethandler(0xf073, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
|
|
|
|
/* 40Mhz Oscillator Enable Disable */
|
|
io_sethandler(0xf072, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
|
|
io_sethandler(0xf472, 1, NULL, NULL, NULL, NULL, wd76c10_write, NULL, dev);
|
|
|
|
/* Lock Status */
|
|
io_sethandler(0xfc72, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
|
|
|
|
/* Cache Flush */
|
|
io_sethandler(0xf872, 1, NULL, wd76c10_read, NULL, NULL, NULL, NULL, dev);
|
|
|
|
dma_ext_mode_init();
|
|
|
|
wd76c10_shadow_recalc(dev);
|
|
wd76c10_refresh_control(dev);
|
|
wd76c10_disk_chip_select(dev);
|
|
return dev;
|
|
}
|
|
|
|
const device_t wd76c10_device = {
|
|
"Western Digital WD76C10",
|
|
"wd76c10",
|
|
0,
|
|
0,
|
|
wd76c10_init,
|
|
wd76c10_close,
|
|
NULL,
|
|
{NULL},
|
|
NULL,
|
|
NULL,
|
|
NULL};
|