f6612fb33b
A lot of clean ups from waltje; Start of a directory structure for the code, thanks to waltje.
311 lines
10 KiB
C
311 lines
10 KiB
C
/*OPTi 82C495 emulation
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This is the chipset used in the AMI386 model*/
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#include "ibm.h"
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#include "cpu/cpu.h"
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#include "io.h"
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#include "mem.h"
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static uint8_t optiregs[0x10];
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static int optireg;
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static void opti495_write(uint16_t addr, uint8_t val, void *p)
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{
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switch (addr)
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{
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case 0x22:
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optireg=val;
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break;
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case 0x24:
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printf("Writing OPTI reg %02X %02X\n",optireg,val);
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if (optireg>=0x20 && optireg<=0x2C)
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{
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optiregs[optireg-0x20]=val;
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if (optireg == 0x21)
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{
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cpu_cache_ext_enabled = val & 0x10;
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cpu_update_waitstates();
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}
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if (optireg == 0x22)
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{
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shadowbios = !(val & 0x80);
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shadowbios_write = val & 0x80;
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if (shadowbios)
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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else
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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}
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}
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break;
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}
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}
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static uint8_t opti495_read(uint16_t addr, void *p)
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{
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switch (addr)
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{
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case 0x24:
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if (optireg>=0x20 && optireg<=0x2C) return optiregs[optireg-0x20];
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break;
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}
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return 0xFF;
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}
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void opti495_init()
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{
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io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
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io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, NULL);
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optiregs[0x22-0x20] = 0x80;
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}
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/*Details for the chipset from Ralph Brown's interrupt list
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This describes the OPTi 82C493, the 82C495 seems similar except there is one
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more register (2C)
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----------P00220024--------------------------
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PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
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Desc: The OPTi 486SXWB contains three chips and is designed for systems
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running at 20, 25 and 33MHz. The chipset includes an 82C493 System
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Controller (SYSC), the 82C392 Data Buffer Controller, and the
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82C206 Integrated peripheral Controller (IPC).
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Note: every access to PORT 0024h must be preceded by a write to PORT 0022h,
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even if the same register is being accessed a second time
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SeeAlso: PORT 0022h"82C206"
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0022 ?W configuration register index (see #P0178)
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0024 RW configuration register data
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(Table P0178)
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Values for OPTi 82C493 System Controller configuration register index:
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20h Control Register 1 (see #P0179)
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21h Control Register 2 (see #P0180)
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22h Shadow RAM Control Register 1 (see #P0181)
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23h Shadow RAM Control Register 2 (see #P0182)
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24h DRAM Control Register 1 (see #P0183)
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25h DRAM Control Register 2 (see #P0184)
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26h Shadow RAM Control Register 3 (see #P0185)
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27h Control Register 3 (see #P0186)
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28h Non-cachable Block 1 Register 1 (see #P0187)
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29h Non-cachable Block 1 Register 2 (see #P0188)
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2Ah Non-cachable Block 2 Register 1 (see #P0187)
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2Bh Non-cachable Block 2 Register 2 (see #P0188)
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Bitfields for OPTi-82C493 Control Register 1:
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Bit(s) Description (Table P0179)
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7-6 Revision of 82C493 (readonly) (default=01)
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5 Burst wait state control
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1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
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0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
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(if bit 5 is set to 1, bit 4 must be set to 0)
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4 Cache memory data buffer output enable control
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0 = disable (default)
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1 = enable
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(must be disabled for frequency <= 33Mhz)
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3 Single Address Latch Enable (ALE)
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0 = disable (default)
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1 = enable
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(if enabled, SYSC will activate single ALE rather than multiples
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during bus conversion cycles)
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2 enable Extra AT Cycle Wait State (default is 0 = disabled)
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1 Emulation keyboard Reset Control
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0 = disable (default)
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1 = enable
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Note: This bit must be enabled in BIOS default value; enabling this
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bit requires HALT instruction to be executed before SYSC
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generates processor reset (CPURST)
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0 enable Alternative Fast Reset (default is 0 = disabled)
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SeeAlso: #P0180,#P0186
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Bitfields for OPTi-82C493 Control Register 2:
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Bit(s) Description (Table P0180)
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7 Master Mode Byte Swap Enable
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0 = disable (default)
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1 = enable
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6 Emulation Keyboard Reset Delay Control
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0 = Generate reset pulse 2us later (default)
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1 = Generate reset pulse immediately
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5 disable Parity Check (default is 0 = enabled)
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4 Cache Enable
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0 = Cache disabled and DRAM burst mode enabled (default)
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1 = Cache enabled and DRAM burst mode disabled
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3-2 Cache Size
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00 64KB (default)
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01 128KB
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10 256KB
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11 512KB
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1 Secondary Cache Read Burst Cycles Control
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0 = 3-1-1-1 cycle (default)
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1 = 2-1-1-1 cycle
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0 Cache Write Wait State Control
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0 = 1 wait state (default)
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1 = 0 wait state
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SeeAlso: #P0179,#P0186
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Bitfields for OPTi-82C493 Shadow RAM Control Register 1:
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Bit(s) Description (Table P0181)
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7 ROM(F0000h - FFFFFh) Enable
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0 = read/write on write-protected DRAM
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1 = read from ROM, write to DRAM (default)
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6 Shadow RAM at D0000h - EFFFFh Area
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0 = disable (default)
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1 = enable
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5 Shadow RAM at E0000h - EFFFFh Area
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0 = disable shadow RAM (default)
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E0000h - EFFFFh ROM is defaulted to reside on XD bus
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1 = enable shadow RAM
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4 enable write-protect for Shadow RAM at D0000h - DFFFFh Area
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0 = disable (default)
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1 = enable
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3 enable write-protect for Shadow RAM at E0000h - EFFFFh Area
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0 = disable (default)
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1 = enable
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2 Hidden refresh enable (with holding CPU)
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(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used)
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1 = disable (default)
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0 = enable
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1 unused
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0 enable Slow Refresh (four times slower than normal refresh)
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(default is 0 = disable)
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SeeAlso: #P0182
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Bitfields for OPTi-82C493 Shadow RAM Control Register 2:
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Bit(s) Description (Table P0182)
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7 enable Shadow RAM at EC000h - EFFFFh area
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6 enable Shadow RAM at E8000h - EBFFFh area
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5 enable Shadow RAM at E4000h - E7FFFh area
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4 enable Shadow RAM at E0000h - E3FFFh area
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3 enable Shadow RAM at DC000h - DFFFFh area
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2 enable Shadow RAM at D8000h - DBFFFh area
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1 enable Shadow RAM at D4000h - D7FFFh area
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0 enable Shadow RAM at D0000h - D3FFFh area
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Note: the default is disabled (0) for all areas
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Bitfields for OPTi-82C493 DRAM Control Register 1:
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Bit(s) Description (Table P0183)
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7 DRAM size
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0 = 256K DRAM mode
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1 = 1M and 4M DRAM mode
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6-4 DRAM types used for bank0 and bank1
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bits 7-4 Bank0 Bank1
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0000 256K x
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0001 256K 256K
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0010 256K 1M
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0011 x x
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01xx x x
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1000 1M x (default)
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1001 1M 1M
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1010 1M 4M
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1011 4M 1M
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1100 4M x
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1101 4M 4M
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111x x x
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3 unused
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2-0 DRAM types used for bank2 and bank3
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bits 7,2-0 Bank2 Bank3
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x000 1M x
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x001 1M 1M
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x010 x x
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x011 4M 1M
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x100 4M x
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x101 4M 4M
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x11x x x (default)
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SeeAlso: #P0184
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Bitfields for OPTi-82C493 DRAM Control Register 2:
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Bit(s) Description (Table P0184)
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7-6 Read cycle additional wait states
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00 not used
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01 = 0
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10 = 1
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11 = 2 (default)
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5-4 Write cycle additional wait states
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00 = 0
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01 = 1
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10 = 2
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11 = 3 (default)
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3 Fast decode enable
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0 = disable fast decode. DRAM base wait states not changed (default)
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1 = enable fast decode. DRAM base wait state is decreased by 1
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Note: This function may be enabled in 20/25Mhz operation to speed up
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DRAM access. If bit 4 of index register 21h (cache enable
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bit) is enabled, this bit is automatically disabled--even if
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set to 1
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2 unused
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1-0 ATCLK selection
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00 ATCLK = CLKI/6 (default)
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01 ATCLK = CLKI/4 (default)
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10 ATCLK = CLKI/3
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11 ATCLK = CLK2I/5 (CLKI * 2 /5)
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Note: bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
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set to 0 when 82C493 is reset.
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SeeAlso: #P0183,#P0185
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Bitfields for OPTi-82C493 Shadow RAM Control Register 3:
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Bit(s) Description (Table P0185)
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7 unused
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6 Shadow RAM copy enable for address C0000h - CFFFFh
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0 = Read/write at AT bus (default)
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1 = Read from AT bus and write into shadow RAM
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5 Shadow write protect at address C0000h - CFFFFh
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0 = Write protect disable (default)
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1 = Write protect enable
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4 enable Shadow RAM at C0000h - CFFFFh
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3 enable Shadow RAM at CC000h - CFFFFh
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2 enable Shadow RAM at C8000h - CBFFFh
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1 enable Shadow RAM at C4000h - C7FFFh
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0 enable Shadow RAM at C0000h - C3FFFh
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Note: the default is disabled (0) for bits 4-0
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SeeAlso: #P0183,#P0184
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Bitfields for OPTi-82C493 Control Register 3:
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Bit(s) Description (Table P0186)
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7 enable NCA# pin to low state (default is 1 = enabled)
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6-5 unused
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4 Video BIOS at C0000h - C8000h non-cacheable
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0 = cacheable
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1 = non-cacheable (default)
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3-0 Cacheable address range for local memory
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0000 0 - 64MB
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0001 0 - 4MB (default)
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0010 0 - 8MB
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0011 0 - 12MB
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0100 0 - 16MB
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0101 0 - 20MB
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0110 0 - 24MB
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0111 0 - 28MB
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1000 0 - 32MB
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1001 0 - 36MB
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1010 0 - 40MB
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1011 0 - 44MB
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1100 0 - 48MB
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1101 0 - 52MB
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1110 0 - 56MB
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1111 0 - 60MB
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Note: If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
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0-2 MB and independent of the value of bits 3-0
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SeeAlso: #P0179,#P0180
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Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
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Bit(s) Description (Table P0187)
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7-5 Size of non-cachable memory block
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000 64K
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001 128K
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010 256K
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011 512K
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1xx disabled (default)
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4-2 unused
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1-0 Address bits 25 and 24 of non-cachable memory block (default = 00)
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Note: this register is used together with configuration register 29h
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(non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
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define a non-cacheable block. The starting address must be a
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multiple of the block size
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SeeAlso: #P0178,#P0188
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Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
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Bit(s) Description (Table P0188)
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7-0 Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
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Note: the block address is forced to be a multiple of the block size by
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ignoring the appropriate number of the least-significant bits
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SeeAlso: #P0178,#P0187
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*/
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