294 lines
5.5 KiB
C
294 lines
5.5 KiB
C
static int
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opMOVD_l_mm_a16(uint32_t fetchdat)
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{
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uint32_t dst;
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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op->l[0] = cpu_state.regs[cpu_rm].l;
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op->l[1] = 0;
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_READ(cpu_state.ea_seg);
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dst = readmeml(easeg, cpu_state.eaaddr);
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if (cpu_state.abrt)
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return 1;
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op->l[0] = dst;
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op->l[1] = 0;
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CLOCK_CYCLES(2);
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}
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MMX_SETEXP(cpu_reg);
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return 0;
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}
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static int
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opMOVD_l_mm_a32(uint32_t fetchdat)
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{
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uint32_t dst;
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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op->l[0] = cpu_state.regs[cpu_rm].l;
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op->l[1] = 0;
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_READ(cpu_state.ea_seg);
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dst = readmeml(easeg, cpu_state.eaaddr);
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if (cpu_state.abrt)
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return 1;
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op->l[0] = dst;
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op->l[1] = 0;
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CLOCK_CYCLES(2);
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}
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MMX_SETEXP(cpu_reg);
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return 0;
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}
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static int
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opMOVD_mm_l_a16(uint32_t fetchdat)
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{
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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cpu_state.regs[cpu_rm].l = op->l[0];
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
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writememl(easeg, cpu_state.eaaddr, op->l[0]);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int
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opMOVD_mm_l_a32(uint32_t fetchdat)
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{
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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cpu_state.regs[cpu_rm].l = op->l[0];
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
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writememl(easeg, cpu_state.eaaddr, op->l[0]);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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/*Cyrix maps both MOVD and SMINT to the same opcode*/
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static int
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opMOVD_mm_l_a16_cx(uint32_t fetchdat)
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{
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const MMX_REG *op;
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if (in_smm)
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return opSMINT(fetchdat);
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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cpu_state.regs[cpu_rm].l = op->l[0];
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
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writememl(easeg, cpu_state.eaaddr, op->l[0]);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int
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opMOVD_mm_l_a32_cx(uint32_t fetchdat)
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{
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const MMX_REG *op;
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if (in_smm)
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return opSMINT(fetchdat);
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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cpu_state.regs[cpu_rm].l = op->l[0];
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
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writememl(easeg, cpu_state.eaaddr, op->l[0]);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int
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opMOVQ_q_mm_a16(uint32_t fetchdat)
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{
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uint64_t dst;
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MMX_REG src;
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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src = MMX_GETREG(cpu_rm);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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op->q = src.q;
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_READ(cpu_state.ea_seg);
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dst = readmemq(easeg, cpu_state.eaaddr);
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if (cpu_state.abrt)
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return 1;
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op->q = dst;
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CLOCK_CYCLES(2);
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}
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MMX_SETEXP(cpu_reg);
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return 0;
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}
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static int
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opMOVQ_q_mm_a32(uint32_t fetchdat)
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{
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uint64_t dst;
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MMX_REG src;
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MMX_REG *op;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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src = MMX_GETREG(cpu_rm);
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op = MMX_GETREGP(cpu_reg);
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if (cpu_mod == 3) {
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op->q = src.q;
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CLOCK_CYCLES(1);
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} else {
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SEG_CHECK_READ(cpu_state.ea_seg);
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dst = readmemq(easeg, cpu_state.eaaddr);
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if (cpu_state.abrt)
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return 1;
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op->q = dst;
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CLOCK_CYCLES(2);
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}
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MMX_SETEXP(cpu_reg);
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return 0;
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}
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static int
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opMOVQ_mm_q_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_REG *dst;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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src = MMX_GETREG(cpu_reg);
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dst = MMX_GETREGP(cpu_rm);
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if (cpu_mod == 3) {
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dst->q = src.q;
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CLOCK_CYCLES(1);
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MMX_SETEXP(cpu_rm);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
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writememq(easeg, cpu_state.eaaddr, src.q);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int
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opMOVQ_mm_q_a32(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_REG *dst;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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src = MMX_GETREG(cpu_reg);
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dst = MMX_GETREGP(cpu_rm);
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if (cpu_mod == 3) {
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dst->q = src.q;
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CLOCK_CYCLES(1);
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MMX_SETEXP(cpu_rm);
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} else {
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 7);
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writememq(easeg, cpu_state.eaaddr, src.q);
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if (cpu_state.abrt)
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return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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