398 lines
8.9 KiB
C
398 lines
8.9 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the UMC 8886xx PCI to ISA Bridge .
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*
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* Note: This chipset has no datasheet, everything were done via
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* reverse engineering the BIOS of various machines using it.
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Tiseno100.
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* Copyright 2021 Miran Grca.
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*/
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/*
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UMC 8886xx Configuration Registers
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Note: PMU functionality is quite basic. There may be Enable/Disable bits, IRQ/SMI picks and it also
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required for 386_common.c to get patched in order to function properly.
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Warning: Register documentation may be inaccurate!
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UMC 8886xx:
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(F: Has No Internal IDE / AF or BF: Has Internal IDE)
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Function 0 Register 43:
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Bits 7-4 PCI IRQ for INTB
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Bits 3-0 PCI IRQ for INTA
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Function 0 Register 44:
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Bits 7-4 PCI IRQ for INTD
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Bits 3-0 PCI IRQ for INTC
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Function 0 Register 46 (corrected by Miran Grca):
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Bit 7: IRQ SMI Request (1: IRQ 15, 0: IRQ 10)
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Bit 6: PMU Trigger(1: By IRQ/0: By SMI)
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Function 0 Register 56:
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Bit 1-0 ISA Bus Speed
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0 0 PCICLK/3
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0 1 PCICLK/4
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1 0 PCICLK/2
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Function 0 Register A2 - non-software SMI# status register
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(documented by Miran Grca):
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Bit 4: I set, graphics card goes into sleep mode
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This register is most likely R/WC
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Function 0 Register A3 (added more details by Miran Grca):
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Bit 7: Unlock SMM
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Bit 6: Software SMI trigger (also doubles as software SMI# status register,
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cleared by writing a 0 to it - see the handler used by Phoenix BIOS'es):
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If Function 0 Register 46 Bit 6 is set, it raises the specified IRQ (15
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or 10) instead.
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Function 0 Register A4:
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Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
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Function 1 Register 4: (UMC 8886AF/8886BF Only!)
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Bit 0: Enable Internal IDE
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/hdd.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/pic.h>
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#include <86box/pci.h>
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#include <86box/chipset.h>
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#define IDE_BIT 0x01
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#ifdef ENABLE_UMC_8886_LOG
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int umc_8886_do_log = ENABLE_UMC_8886_LOG;
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static void
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umc_8886_log(const char *fmt, ...)
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{
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va_list ap;
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if (umc_8886_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define umc_8886_log(fmt, ...)
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#endif
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/* PCI IRQ Flags */
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#define INTA (PCI_INTA + (2 * !(addr & 1)))
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#define INTB (PCI_INTB + (2 * !(addr & 1)))
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#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED)
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#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED)
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/* Disable Internal IDE Flag needed for the AF or BF Southbridge variant */
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#define HAS_IDE dev->has_ide
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/* Southbridge Revision */
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#define SB_ID dev->sb_id
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typedef struct umc_8886_t
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{
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uint8_t max_func, /* Last function number */
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pci_conf_sb[2][256]; /* PCI Registers */
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uint16_t sb_id; /* Southbridge Revision */
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int has_ide; /* Check if Southbridge Revision is AF or F */
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} umc_8886_t;
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static void
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umc_8886_ide_handler(int status)
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{
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ide_pri_disable();
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ide_sec_disable();
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if (status) {
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ide_pri_enable();
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ide_sec_enable();
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}
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}
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static void
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umc_8886_write(int func, int addr, uint8_t val, void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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if (func <= dev->max_func) switch (func) {
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case 0: /* PCI to ISA Bridge */
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umc_8886_log("UM8886: dev->regs[%02x] = %02x POST %02x\n", addr, val, inb(0x80));
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switch (addr) {
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case 0x04: case 0x05:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x07:
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dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
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break;
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case 0x0c: case 0x0d:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x40: case 0x41:
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case 0x42:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x43: case 0x44:
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dev->pci_conf_sb[func][addr] = val;
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pci_set_irq_routing(INTA, IRQRECALCA);
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pci_set_irq_routing(INTB, IRQRECALCB);
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break;
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case 0x45:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x46:
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/* Bit 6 seems to be the IRQ/SMI# toggle, 1 = IRQ, 0 = SMI#. */
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x47:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x50: case 0x51: case 0x52: case 0x53:
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case 0x54: case 0x55:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0x56:
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dev->pci_conf_sb[func][addr] = val;
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switch (val & 2) {
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case 0:
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cpu_set_isa_pci_div(3);
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break;
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case 1:
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cpu_set_isa_pci_div(4);
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break;
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case 2:
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cpu_set_isa_pci_div(2);
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break;
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}
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break;
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case 0x57:
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case 0x70 ... 0x76:
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case 0x80: case 0x81:
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case 0x90 ... 0x92:
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case 0xa0 ... 0xa1:
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0xa2:
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dev->pci_conf_sb[func][addr] &= ~val;
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break;
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case 0xa3:
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/* SMI Provocation (Bit 7 Enable SMM + Bit 6 Software SMI) */
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if (((val & 0xc0) == 0xc0) && !(dev->pci_conf_sb[0][0xa3] & 0x40)) {
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if (dev->pci_conf_sb[0][0x46] & 0x40)
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picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10));
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else
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smi_line = 1;
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dev->pci_conf_sb[0][0xa3] |= 0x04;
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}
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dev->pci_conf_sb[func][addr] = val;
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break;
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case 0xa4:
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dev->pci_conf_sb[func][addr] = val;
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cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2));
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break;
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case 0xa5 ... 0xa8:
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dev->pci_conf_sb[func][addr] = val;
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break;
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}
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break;
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case 1: /* IDE Controller */
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umc_8886_log("UM8886-IDE: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80));
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switch (addr) {
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case 0x04:
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dev->pci_conf_sb[func][addr] = val;
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umc_8886_ide_handler(val & 1);
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break;
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case 0x07:
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dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
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break;
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case 0x3c:
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case 0x40: case 0x41:
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dev->pci_conf_sb[func][addr] = val;
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break;
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}
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break;
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}
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}
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static uint8_t
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umc_8886_read(int func, int addr, void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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uint8_t ret = 0xff;
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if (func <= dev->max_func)
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ret = dev->pci_conf_sb[func][addr];
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return ret;
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}
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static void
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umc_8886_reset(void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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memset(dev->pci_conf_sb[0], 0x00, sizeof(dev->pci_conf_sb[0]));
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memset(dev->pci_conf_sb[1], 0x00, sizeof(dev->pci_conf_sb[1]));
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dev->pci_conf_sb[0][0] = 0x60; /* UMC */
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dev->pci_conf_sb[0][1] = 0x10;
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dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */
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dev->pci_conf_sb[0][3] = ((SB_ID >> 8) & 0xff);
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dev->pci_conf_sb[0][4] = 0x0f;
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dev->pci_conf_sb[0][7] = 2;
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dev->pci_conf_sb[0][8] = 0x0e;
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dev->pci_conf_sb[0][0x09] = 0x00;
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dev->pci_conf_sb[0][0x0a] = 0x01;
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dev->pci_conf_sb[0][0x0b] = 0x06;
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dev->pci_conf_sb[0][0x40] = 1;
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dev->pci_conf_sb[0][0x41] = 6;
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dev->pci_conf_sb[0][0x42] = 8;
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dev->pci_conf_sb[0][0x43] = 0x9a;
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dev->pci_conf_sb[0][0x44] = 0xbc;
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dev->pci_conf_sb[0][0x45] = 4;
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dev->pci_conf_sb[0][0x47] = 0x40;
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dev->pci_conf_sb[0][0x50] = 1;
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dev->pci_conf_sb[0][0x51] = 3;
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dev->pci_conf_sb[0][0xa8] = 0x20;
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if (HAS_IDE) {
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dev->pci_conf_sb[1][0] = 0x60; /* UMC */
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dev->pci_conf_sb[1][1] = 0x10;
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dev->pci_conf_sb[1][2] = 0x3a; /* 8886BF IDE */
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dev->pci_conf_sb[1][3] = 0x67;
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dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
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dev->pci_conf_sb[1][8] = 0x10;
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dev->pci_conf_sb[1][0x09] = 0x0f;
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dev->pci_conf_sb[1][0x0a] = dev->pci_conf_sb[1][0x0b] = 1;
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umc_8886_ide_handler(1);
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}
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for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
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pci_set_irq_routing(i, PCI_IRQ_DISABLED);
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cpu_set_isa_pci_div(3);
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cpu_set_pci_speed(cpu_busspeed / 2);
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}
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static void
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umc_8886_close(void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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free(dev);
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}
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static void *
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umc_8886_init(const device_t *info)
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{
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umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t));
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memset(dev, 0, sizeof(umc_8886_t));
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dev->has_ide = !!(info->local == 0x886a);
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pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev); /* Device 12: UMC 8886xx */
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/* Add IDE if UM8886AF variant */
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if (HAS_IDE)
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device_add(&ide_pci_2ch_device);
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dev->max_func = (HAS_IDE) ? 1 : 0;
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/* Get the Southbridge Revision */
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SB_ID = info->local;
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umc_8886_reset(dev);
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return dev;
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}
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const device_t umc_8886f_device = {
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"UMC 8886F",
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DEVICE_PCI,
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0x8886,
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umc_8886_init, umc_8886_close, umc_8886_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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const device_t umc_8886af_device = {
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"UMC 8886AF/8886BF",
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DEVICE_PCI,
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0x886a,
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umc_8886_init, umc_8886_close, umc_8886_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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