112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/*
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* VARCem Virtual ARchaeological Computer EMulator.
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* An emulator of (mostly) x86-based PC systems and devices,
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* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
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* spanning the era between 1981 and 1995.
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*
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* This file is part of the VARCem Project.
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*
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* Definitions for the Intel DMA controller.
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*
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*
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*
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* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
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* Miran Grca, <mgrca8@gmail.com>
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* Sarah Walker, <tommowalker@tommowalker.co.uk>
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*
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* Copyright 2017-2020 Fred N. van Kempen.
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* Copyright 2016-2020 Miran Grca.
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* Copyright 2008-2020 Sarah Walker.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the:
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*
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* Free Software Foundation, Inc.
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* 59 Temple Place - Suite 330
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* Boston, MA 02111-1307
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* USA.
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*/
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#ifndef EMU_DMA_H
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# define EMU_DMA_H
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#define DMA_NODATA -1
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#define DMA_OVER 0x10000
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#define DMA_VERIFY 0x20000
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typedef struct {
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uint8_t m, mode, page, stat,
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stat_rq, command,
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ps2_mode, arb_level,
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sg_command, sg_status,
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ptr0, enabled,
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ext_mode, page_l,
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page_h, pad;
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uint16_t cb, io_addr,
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base, transfer_mode;
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uint32_t ptr, ptr_cur,
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addr,
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ab, ac;
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int cc, wp,
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size, count,
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eot;
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} dma_t;
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extern dma_t dma[8];
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extern uint8_t dma_e;
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extern uint8_t dma_m;
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extern void dma_init(void);
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extern void dma16_init(void);
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extern void ps2_dma_init(void);
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extern void dma_reset(void);
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extern int dma_mode(int channel);
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extern void readdma0(void);
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extern int readdma1(void);
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extern uint8_t readdma2(void);
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extern int readdma3(void);
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extern void writedma2(uint8_t temp);
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extern int dma_get_drq(int channel);
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extern void dma_set_drq(int channel, int set);
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extern int dma_channel_read(int channel);
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extern int dma_channel_write(int channel, uint16_t val);
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extern void dma_alias_set(void);
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extern void dma_alias_set_piix(void);
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extern void dma_alias_remove(void);
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extern void dma_alias_remove_piix(void);
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extern void dma_bm_read(uint32_t PhysAddress, uint8_t *DataRead, uint32_t TotalSize, int TransferSize);
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extern void dma_bm_write(uint32_t PhysAddress, const uint8_t *DataWrite, uint32_t TotalSize, int TransferSize);
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void dma_set_params(uint8_t advanced, uint32_t mask);
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void dma_set_mask(uint32_t mask);
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void dma_set_at(uint8_t at);
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void dma_ext_mode_init(void);
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void dma_high_page_init(void);
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void dma_remove_sg(void);
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void dma_set_sg_base(uint8_t sg_base);
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#endif /*EMU_DMA_H*/
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