381 lines
11 KiB
C
381 lines
11 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Contaq/Cypress 82C596(A) and 597 chipsets.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/smram.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_CONTAQ_82C59X_LOG
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int contaq_82c59x_do_log = ENABLE_CONTAQ_82C59X_LOG;
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static void
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contaq_82c59x_log(const char *fmt, ...)
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{
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va_list ap;
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if (contaq_82c59x_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define contaq_82c59x_log(fmt, ...)
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#endif
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typedef struct mem_remapping_t {
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uint32_t phys;
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uint32_t virt;
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} mem_remapping_t;
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typedef struct contaq_82c59x_t {
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uint8_t index;
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uint8_t green;
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uint8_t smi_status_set;
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uint8_t regs[256];
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uint8_t smi_status[2];
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smram_t *smram[2];
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} contaq_82c59x_t;
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static void
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contaq_82c59x_isa_speed_recalc(contaq_82c59x_t *dev)
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{
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if (dev->regs[0x1c] & 0x02)
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cpu_set_isa_speed(7159091);
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else {
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/* TODO: ISA clock dividers for 386 and alt. 486. */
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switch (dev->regs[0x10] & 0x03) {
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case 0x00:
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cpu_set_isa_speed(cpu_busspeed / 4);
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break;
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case 0x01:
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cpu_set_isa_speed(cpu_busspeed / 6);
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break;
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case 0x02:
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cpu_set_isa_speed(cpu_busspeed / 8);
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break;
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case 0x03:
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cpu_set_isa_speed(cpu_busspeed / 5);
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break;
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default:
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break;
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}
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}
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}
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static void
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contaq_82c59x_shadow_recalc(contaq_82c59x_t *dev)
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{
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uint32_t i;
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uint32_t base;
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uint8_t bit;
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shadowbios = shadowbios_write = 0;
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/* F0000-FFFFF */
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if (dev->regs[0x15] & 0x80) {
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shadowbios |= 1;
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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} else {
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shadowbios_write |= 1;
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mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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}
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/* C0000-CFFFF */
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if (dev->regs[0x15] & 0x01)
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mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else {
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for (i = 0; i < 4; i++) {
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base = 0xc0000 + (i << 14);
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bit = 1 << (i + 2);
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if (dev->regs[0x15] & bit) {
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if (dev->regs[0x15] & 0x02)
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mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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else
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mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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} else
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mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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if (dev->green) {
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/* D0000-DFFFF */
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if (dev->regs[0x6e] & 0x01)
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mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else {
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for (i = 0; i < 4; i++) {
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base = 0xd0000 + (i << 14);
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bit = 1 << (i + 2);
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if (dev->regs[0x6e] & bit) {
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if (dev->regs[0x6e] & 0x02)
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mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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else
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mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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} else
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mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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/* E0000-EFFFF */
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if (dev->regs[0x6f] & 0x01)
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mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else {
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for (i = 0; i < 4; i++) {
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base = 0xe0000 + (i << 14);
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bit = 1 << (i + 2);
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if (dev->regs[0x6f] & bit) {
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shadowbios |= 1;
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if (dev->regs[0x6f] & 0x02)
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mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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else {
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shadowbios_write |= 1;
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mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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}
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} else
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mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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}
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}
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static void
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contaq_82c59x_smram_recalc(contaq_82c59x_t *dev)
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{
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smram_disable(dev->smram[1]);
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if (dev->regs[0x70] & 0x04)
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smram_enable(dev->smram[1], 0x00040000, 0x000a0000, 0x00020000, 1, 1);
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}
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static void
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contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
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{
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contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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contaq_82c59x_log("Contaq 82C59x: dev->regs[%02x] = %02x\n", dev->index, val);
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if ((dev->index >= 0x60) && !dev->green)
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return;
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switch (dev->index) {
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/* Registers common to 82C596(A) and 82C597. */
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case 0x10:
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dev->regs[dev->index] = val;
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contaq_82c59x_isa_speed_recalc(dev);
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break;
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case 0x11:
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dev->regs[dev->index] = val;
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cpu_cache_int_enabled = !!(val & 0x01);
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cpu_update_waitstates();
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break;
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case 0x12:
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case 0x13:
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dev->regs[dev->index] = val;
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break;
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case 0x14:
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dev->regs[dev->index] = val;
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reset_on_hlt = !!(val & 0x80);
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break;
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case 0x15:
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dev->regs[dev->index] = val;
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contaq_82c59x_shadow_recalc(dev);
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break;
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case 0x16 ... 0x1b:
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dev->regs[dev->index] = val;
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break;
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case 0x1c:
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/* TODO: What's NPRST (generated if bit 3 is set)? */
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dev->regs[dev->index] = val;
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contaq_82c59x_isa_speed_recalc(dev);
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break;
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case 0x1d ... 0x1f:
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dev->regs[dev->index] = val;
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break;
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/* Green (82C597-specific) registers. */
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case 0x60 ... 0x63:
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dev->regs[dev->index] = val;
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break;
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case 0x64:
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dev->regs[dev->index] = val;
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if (val & 0x80) {
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if (dev->regs[0x65] & 0x80)
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smi_raise();
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dev->smi_status[0] |= 0x10;
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}
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break;
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case 0x65 ... 0x69:
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dev->regs[dev->index] = val;
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break;
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case 0x6a:
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dev->regs[dev->index] = val;
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dev->smi_status_set = !!(val & 0x80);
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break;
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case 0x6b ... 0x6d:
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dev->regs[dev->index] = val;
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break;
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case 0x6e:
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case 0x6f:
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dev->regs[dev->index] = val;
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contaq_82c59x_shadow_recalc(dev);
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break;
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case 0x70:
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dev->regs[dev->index] = val;
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contaq_82c59x_smram_recalc(dev);
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break;
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case 0x71 ... 0x79:
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dev->regs[dev->index] = val;
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break;
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case 0x7b:
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case 0x7c:
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dev->regs[dev->index] = val;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static uint8_t
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contaq_82c59x_read(uint16_t addr, void *priv)
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{
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contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
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uint8_t ret = 0xff;
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if (addr == 0x23) {
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if (dev->index == 0x6a) {
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ret = dev->smi_status[dev->smi_status_set];
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/* I assume it's cleared on read. */
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dev->smi_status[dev->smi_status_set] = 0x00;
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} else
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ret = dev->regs[dev->index];
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}
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return ret;
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}
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static void
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contaq_82c59x_close(void *priv)
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{
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contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
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if (dev->green) {
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smram_del(dev->smram[1]);
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smram_del(dev->smram[0]);
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}
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free(dev);
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}
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static void *
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contaq_82c59x_init(const device_t *info)
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{
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contaq_82c59x_t *dev = (contaq_82c59x_t *) malloc(sizeof(contaq_82c59x_t));
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memset(dev, 0x00, sizeof(contaq_82c59x_t));
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dev->green = info->local;
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io_sethandler(0x0022, 0x0002, contaq_82c59x_read, NULL, NULL, contaq_82c59x_write, NULL, NULL, dev);
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contaq_82c59x_isa_speed_recalc(dev);
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cpu_cache_int_enabled = 0;
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cpu_update_waitstates();
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reset_on_hlt = 0;
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contaq_82c59x_shadow_recalc(dev);
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if (dev->green) {
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/* SMRAM 0: Fixed A0000-BFFFF to A0000-BFFFF DRAM. */
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dev->smram[0] = smram_add();
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smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x00020000, 0, 1);
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/* SMRAM 1: Optional. */
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dev->smram[1] = smram_add();
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contaq_82c59x_smram_recalc(dev);
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}
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return dev;
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}
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const device_t contaq_82c596a_device = {
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.name = "Contaq 82C596A",
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.internal_name = "contaq_82c596a",
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.flags = 0,
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.local = 0,
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.init = contaq_82c59x_init,
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.close = contaq_82c59x_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t contaq_82c597_device = {
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.name = "Contaq 82C597",
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.internal_name = "contaq_82c597",
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.flags = 0,
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.local = 1,
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.init = contaq_82c59x_init,
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.close = contaq_82c59x_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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