dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
284 lines
13 KiB
C
284 lines
13 KiB
C
static uint32_t ropPUSH_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-2);
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host_reg = LOAD_REG_W(opcode & 7);
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MEM_STORE_ADDR_EA_W(&_ss, host_reg);
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SP_MODIFY(-2);
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return op_pc;
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}
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static uint32_t ropPUSH_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-4);
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host_reg = LOAD_REG_L(opcode & 7);
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MEM_STORE_ADDR_EA_L(&_ss, host_reg);
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SP_MODIFY(-4);
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return op_pc;
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}
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static uint32_t ropPUSH_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint16_t imm = fetchdat & 0xffff;
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-2);
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host_reg = LOAD_REG_IMM(imm);
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MEM_STORE_ADDR_EA_W(&_ss, host_reg);
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SP_MODIFY(-2);
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return op_pc+2;
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}
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static uint32_t ropPUSH_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint32_t imm = fastreadl(cs + op_pc);
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-4);
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host_reg = LOAD_REG_IMM(imm);
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MEM_STORE_ADDR_EA_L(&_ss, host_reg);
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SP_MODIFY(-4);
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return op_pc+4;
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}
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static uint32_t ropPUSH_imm_b16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint16_t imm = fetchdat & 0xff;
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int host_reg;
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if (imm & 0x80)
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imm |= 0xff00;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-2);
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host_reg = LOAD_REG_IMM(imm);
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MEM_STORE_ADDR_EA_W(&_ss, host_reg);
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SP_MODIFY(-2);
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return op_pc+1;
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}
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static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint32_t imm = fetchdat & 0xff;
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int host_reg;
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if (imm & 0x80)
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imm |= 0xffffff00;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-4);
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host_reg = LOAD_REG_IMM(imm);
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MEM_STORE_ADDR_EA_L(&_ss, host_reg);
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SP_MODIFY(-4);
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return op_pc+1;
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}
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static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_W(&_ss);
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SP_MODIFY(2);
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STORE_REG_TARGET_W_RELEASE(0, opcode & 7);
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return op_pc;
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}
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static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_L(&_ss);
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SP_MODIFY(4);
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STORE_REG_TARGET_L_RELEASE(0, opcode & 7);
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return op_pc;
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}
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static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_W(&_ss);
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STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
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SP_MODIFY(2);
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return -1;
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}
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static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_L(&_ss);
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STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
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SP_MODIFY(4);
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return -1;
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}
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static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint16_t offset = fetchdat & 0xffff;
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_W(&_ss);
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STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
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SP_MODIFY(2+offset);
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return -1;
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}
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static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint16_t offset = fetchdat & 0xffff;
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(0);
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MEM_LOAD_ADDR_EA_L(&_ss);
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STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.pc, 0);
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SP_MODIFY(4+offset);
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return -1;
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}
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static uint32_t ropCALL_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint16_t offset = fetchdat & 0xffff;
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-2);
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host_reg = LOAD_REG_IMM(op_pc+2);
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MEM_STORE_ADDR_EA_W(&_ss, host_reg);
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SP_MODIFY(-2);
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, (op_pc+2+offset) & 0xffff);
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return -1;
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}
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static uint32_t ropCALL_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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uint32_t offset = fastreadl(cs + op_pc);
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_STACK_TO_EA(-4);
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host_reg = LOAD_REG_IMM(op_pc+4);
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MEM_STORE_ADDR_EA_L(&_ss, host_reg);
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SP_MODIFY(-4);
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.pc, op_pc+4+offset);
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return -1;
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}
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static uint32_t ropLEAVE_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_EBP_TO_EA(0);
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MEM_LOAD_ADDR_EA_W(&_ss);
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host_reg = LOAD_REG_W(REG_BP); /*SP = BP + 2*/
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ADD_HOST_REG_IMM_W(host_reg, 2);
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STORE_REG_TARGET_W_RELEASE(host_reg, REG_SP);
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STORE_REG_TARGET_W_RELEASE(0, REG_BP); /*BP = POP_W()*/
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return op_pc;
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}
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static uint32_t ropLEAVE_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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LOAD_EBP_TO_EA(0);
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MEM_LOAD_ADDR_EA_L(&_ss);
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host_reg = LOAD_REG_L(REG_EBP); /*ESP = EBP + 4*/
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ADD_HOST_REG_IMM(host_reg, 4);
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STORE_REG_TARGET_L_RELEASE(host_reg, REG_ESP);
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STORE_REG_TARGET_L_RELEASE(0, REG_EBP); /*EBP = POP_L()*/
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return op_pc;
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}
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#define ROP_PUSH_SEG(seg) \
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static uint32_t ropPUSH_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int host_reg; \
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\
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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LOAD_STACK_TO_EA(-2); \
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host_reg = LOAD_VAR_W((uintptr_t)&seg); \
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MEM_STORE_ADDR_EA_W(&_ss, host_reg); \
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SP_MODIFY(-2); \
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\
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return op_pc; \
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} \
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static uint32_t ropPUSH_ ## seg ## _32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int host_reg; \
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\
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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LOAD_STACK_TO_EA(-4); \
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host_reg = LOAD_VAR_W((uintptr_t)&seg); \
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MEM_STORE_ADDR_EA_L(&_ss, host_reg); \
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SP_MODIFY(-4); \
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\
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return op_pc; \
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}
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ROP_PUSH_SEG(CS)
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ROP_PUSH_SEG(DS)
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ROP_PUSH_SEG(ES)
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ROP_PUSH_SEG(FS)
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ROP_PUSH_SEG(GS)
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ROP_PUSH_SEG(SS)
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#define ROP_POP_SEG(seg, rseg) \
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static uint32_t ropPOP_ ## seg ## _16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int host_reg; \
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\
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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LOAD_STACK_TO_EA(0); \
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MEM_LOAD_ADDR_EA_W(&_ss); \
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LOAD_SEG(0, &rseg); \
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SP_MODIFY(2); \
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\
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return op_pc; \
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} \
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static uint32_t ropPOP_ ## seg ## _32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int host_reg; \
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\
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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LOAD_STACK_TO_EA(0); \
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MEM_LOAD_ADDR_EA_W(&_ss); \
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LOAD_SEG(0, &rseg); \
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SP_MODIFY(4); \
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\
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return op_pc; \
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}
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ROP_POP_SEG(DS, _ds)
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ROP_POP_SEG(ES, _es)
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ROP_POP_SEG(FS, _fs)
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ROP_POP_SEG(GS, _gs)
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