1485 lines
48 KiB
C
1485 lines
48 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implement a more-or-less defacto-standard RTC/NVRAM.
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*
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* When IBM released the PC/AT machine, it came standard with a
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* battery-backed RTC chip to keep the time of day, something
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* that was optional on standard PC's with a myriad variants
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* being put on the market, often on cheap multi-I/O cards.
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*
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* The PC/AT had an on-board DS12885-series chip ("the black
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* block") which was an RTC/clock chip with onboard oscillator
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* and a backup battery (hence the big size.) The chip also had
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* a small amount of RAM bytes available to the user, which was
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* used by IBM's ROM BIOS to store machine configuration data.
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* Later versions and clones used the 12886 and/or 1288(C)7
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* series, or the MC146818 series, all with an external battery.
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* Many of those batteries would create corrosion issues later
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* on in mainboard life...
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*
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* Since then, pretty much any PC has an implementation of that
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* device, which became known as the "nvr" or "cmos".
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*
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* NOTES Info extracted from the data sheets:
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*
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* * The century register at location 32h is a BCD register
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* designed to automatically load the BCD value 20 as the
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* year register changes from 99 to 00. The MSB of this
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* register is not affected when the load of 20 occurs,
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* and remains at the value written by the user.
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*
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* * Rate Selector (RS3:RS0)
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* These four rate-selection bits select one of the 13
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* taps on the 15-stage divider or disable the divider
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* output. The tap selected can be used to generate an
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* output square wave (SQW pin) and/or a periodic interrupt.
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*
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* The user can do one of the following:
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* - enable the interrupt with the PIE bit;
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* - enable the SQW output pin with the SQWE bit;
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* - enable both at the same time and the same rate; or
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* - enable neither.
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*
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* Table 3 lists the periodic interrupt rates and the square
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* wave frequencies that can be chosen with the RS bits.
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* These four read/write bits are not affected by !RESET.
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*
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* * Oscillator (DV2:DV0)
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* These three bits are used to turn the oscillator on or
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* off and to reset the countdown chain. A pattern of 010
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* is the only combination of bits that turn the oscillator
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* on and allow the RTC to keep time. A pattern of 11x
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* enables the oscillator but holds the countdown chain in
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* reset. The next update occurs at 500ms after a pattern
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* of 010 is written to DV0, DV1, and DV2.
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*
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* * Update-In-Progress (UIP)
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* This bit is a status flag that can be monitored. When the
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* UIP bit is a 1, the update transfer occurs soon. When
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* UIP is a 0, the update transfer does not occur for at
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* least 244us. The time, calendar, and alarm information
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* in RAM is fully available for access when the UIP bit
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* is 0. The UIP bit is read-only and is not affected by
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* !RESET. Writing the SET bit in Register B to a 1
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* inhibits any update transfer and clears the UIP status bit.
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*
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* * Daylight Saving Enable (DSE)
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* This bit is a read/write bit that enables two daylight
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* saving adjustments when DSE is set to 1. On the first
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* Sunday in April (or the last Sunday in April in the
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* MC146818A), the time increments from 1:59:59 AM to
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* 3:00:00 AM. On the last Sunday in October when the time
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* first reaches 1:59:59 AM, it changes to 1:00:00 AM.
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*
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* When DSE is enabled, the internal logic test for the
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* first/last Sunday condition at midnight. If the DSE bit
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* is not set when the test occurs, the daylight saving
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* function does not operate correctly. These adjustments
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* do not occur when the DSE bit is 0. This bit is not
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* affected by internal functions or !RESET.
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*
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* * 24/12
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* The 24/12 control bit establishes the format of the hours
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* byte. A 1 indicates the 24-hour mode and a 0 indicates
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* the 12-hour mode. This bit is read/write and is not
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* affected by internal functions or !RESET.
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*
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* * Data Mode (DM)
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* This bit indicates whether time and calendar information
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* is in binary or BCD format. The DM bit is set by the
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* program to the appropriate format and can be read as
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* required. This bit is not modified by internal functions
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* or !RESET. A 1 in DM signifies binary data, while a 0 in
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* DM specifies BCD data.
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*
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* * Square-Wave Enable (SQWE)
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* When this bit is set to 1, a square-wave signal at the
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* frequency set by the rate-selection bits RS3-RS0 is driven
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* out on the SQW pin. When the SQWE bit is set to 0, the
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* SQW pin is held low. SQWE is a read/write bit and is
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* cleared by !RESET. SQWE is low if disabled, and is high
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* impedance when VCC is below VPF. SQWE is cleared to 0 on
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* !RESET.
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*
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* * Update-Ended Interrupt Enable (UIE)
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* This bit is a read/write bit that enables the update-end
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* flag (UF) bit in Register C to assert !IRQ. The !RESET
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* pin going low or the SET bit going high clears the UIE bit.
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* The internal functions of the device do not affect the UIE
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* bit, but is cleared to 0 on !RESET.
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*
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* * Alarm Interrupt Enable (AIE)
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* This bit is a read/write bit that, when set to 1, permits
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* the alarm flag (AF) bit in Register C to assert !IRQ. An
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* alarm interrupt occurs for each second that the three time
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* bytes equal the three alarm bytes, including a don't-care
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* alarm code of binary 11XXXXXX. The AF bit does not
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* initiate the !IRQ signal when the AIE bit is set to 0.
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* The internal functions of the device do not affect the AIE
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* bit, but is cleared to 0 on !RESET.
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*
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* * Periodic Interrupt Enable (PIE)
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* The PIE bit is a read/write bit that allows the periodic
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* interrupt flag (PF) bit in Register C to drive the !IRQ pin
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* low. When the PIE bit is set to 1, periodic interrupts are
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* generated by driving the !IRQ pin low at a rate specified
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* by the RS3-RS0 bits of Register A. A 0 in the PIE bit
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* blocks the !IRQ output from being driven by a periodic
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* interrupt, but the PF bit is still set at the periodic
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* rate. PIE is not modified b any internal device functions,
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* but is cleared to 0 on !RESET.
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*
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* * SET
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* When the SET bit is 0, the update transfer functions
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* normally by advancing the counts once per second. When
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* the SET bit is written to 1, any update transfer is
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* inhibited, and the program can initialize the time and
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* calendar bytes without an update occurring in the midst of
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* initializing. Read cycles can be executed in a similar
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* manner. SET is a read/write bit and is not affected by
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* !RESET or internal functions of the device.
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*
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* * Update-Ended Interrupt Flag (UF)
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* This bit is set after each update cycle. When the UIE
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* bit is set to 1, the 1 in UF causes the IRQF bit to be
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* a 1, which asserts the !IRQ pin. This bit can be
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* cleared by reading Register C or with a !RESET.
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*
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* * Alarm Interrupt Flag (AF)
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* A 1 in the AF bit indicates that the current time has
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* matched the alarm time. If the AIE bit is also 1, the
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* !IRQ pin goes low and a 1 appears in the IRQF bit. This
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* bit can be cleared by reading Register C or with a
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* !RESET.
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*
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* * Periodic Interrupt Flag (PF)
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* This bit is read-only and is set to 1 when an edge is
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* detected on the selected tap of the divider chain. The
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* RS3 through RS0 bits establish the periodic rate. PF is
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* set to 1 independent of the state of the PIE bit. When
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* both PF and PIE are 1s, the !IRQ signal is active and
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* sets the IRQF bit. This bit can be cleared by reading
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* Register C or with a !RESET.
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*
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* * Interrupt Request Flag (IRQF)
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* The interrupt request flag (IRQF) is set to a 1 when one
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* or more of the following are true:
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* - PF == PIE == 1
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* - AF == AIE == 1
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* - UF == UIE == 1
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* Any time the IRQF bit is a 1, the !IRQ pin is driven low.
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* All flag bits are cleared after Register C is read by the
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* program or when the !RESET pin is low.
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*
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* * Valid RAM and Time (VRT)
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* This bit indicates the condition of the battery connected
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* to the VBAT pin. This bit is not writeable and should
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* always be 1 when read. If a 0 is ever present, an
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* exhausted internal lithium energy source is indicated and
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* both the contents of the RTC data and RAM data are
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* questionable. This bit is unaffected by !RESET.
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*
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* This file implements a generic version of the RTC/NVRAM chip,
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* including the later update (DS12887A) which implemented a
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* "century" register to be compatible with Y2K.
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*
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*
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*
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* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
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* Miran Grca, <mgrca8@gmail.com>
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* Mahod,
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*
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* Copyright 2017-2020 Fred N. van Kempen.
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* Copyright 2016-2020 Miran Grca.
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* Copyright 2016-2020 Mahod.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the:
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*
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* Free Software Foundation, Inc.
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* 59 Temple Place - Suite 330
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* Boston, MA 02111-1307
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* USA.
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include <time.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/machine.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/rom.h>
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#include <86box/device.h>
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#include <86box/nvr.h>
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/* RTC registers and bit definitions. */
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#define RTC_SECONDS 0
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#define RTC_ALSECONDS 1
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#define AL_DONTCARE 0xc0 /* Alarm time is not set */
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#define RTC_MINUTES 2
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#define RTC_ALMINUTES 3
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#define RTC_HOURS 4
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#define RTC_AMPM 0x80 /* PM flag if 12h format in use */
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#define RTC_ALHOURS 5
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#define RTC_DOW 6
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#define RTC_DOM 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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#define RTC_REGA 10
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#define REGA_UIP 0x80
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#define REGA_DV2 0x40
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#define REGA_DV1 0x20
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#define REGA_DV0 0x10
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#define REGA_DV 0x70
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#define REGA_RS3 0x08
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#define REGA_RS2 0x04
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#define REGA_RS1 0x02
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#define REGA_RS0 0x01
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#define REGA_RS 0x0f
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#define RTC_REGB 11
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#define REGB_SET 0x80
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#define REGB_PIE 0x40
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#define REGB_AIE 0x20
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#define REGB_UIE 0x10
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#define REGB_SQWE 0x08
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#define REGB_DM 0x04
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#define REGB_2412 0x02
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#define REGB_DSE 0x01
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#define RTC_REGC 12
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#define REGC_IRQF 0x80
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#define REGC_PF 0x40
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#define REGC_AF 0x20
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#define REGC_UF 0x10
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#define RTC_REGD 13
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#define REGD_VRT 0x80
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#define RTC_CENTURY_AT 0x32 /* century register for AT etc */
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#define RTC_CENTURY_PS 0x37 /* century register for PS/1 PS/2 */
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#define RTC_CENTURY_ELT 0x1A /* century register for Epson Equity LT */
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#define RTC_ALDAY 0x7D /* VIA VT82C586B - alarm day */
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#define RTC_ALMONTH 0x7E /* VIA VT82C586B - alarm month */
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#define RTC_CENTURY_VIA 0x7F /* century register for VIA VT82C586B */
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#define RTC_ALDAY_SIS 0x7E /* Day of Month Alarm for SiS */
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#define RTC_ALMONT_SIS 0x7F /* Month Alarm for SiS */
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#define RTC_REGS 14 /* number of registers */
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#define FLAG_NO_NMI 0x01
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#define FLAG_AMI_1992_HACK 0x02
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#define FLAG_AMI_1994_HACK 0x04
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#define FLAG_AMI_1995_HACK 0x08
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#define FLAG_P6RP4_HACK 0x10
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#define FLAG_PIIX4 0x20
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#define FLAG_MULTI_BANK 0x40
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#define FLAG_MARTIN_HACK 0x80
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typedef struct local_t {
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int8_t stat;
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uint8_t cent;
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uint8_t def;
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uint8_t flags;
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uint8_t read_addr;
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uint8_t wp_0d;
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uint8_t wp_32;
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uint8_t irq_state;
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uint8_t smi_status;
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uint8_t wp[2];
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uint8_t bank[8];
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uint8_t *lock;
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int16_t count;
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int16_t state;
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uint16_t addr[8];
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int32_t smi_enable;
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uint64_t ecount;
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uint64_t rtc_time;
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pc_timer_t update_timer;
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pc_timer_t rtc_timer;
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} local_t;
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static uint8_t nvr_at_inited = 0;
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/* Get the current NVR time. */
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static void
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time_get(nvr_t *nvr, struct tm *tm)
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{
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const local_t *local = (local_t *) nvr->data;
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int8_t temp;
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if (nvr->regs[RTC_REGB] & REGB_DM) {
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/* NVR is in Binary data mode. */
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tm->tm_sec = nvr->regs[RTC_SECONDS];
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tm->tm_min = nvr->regs[RTC_MINUTES];
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temp = nvr->regs[RTC_HOURS];
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tm->tm_wday = (nvr->regs[RTC_DOW] - 1);
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tm->tm_mday = nvr->regs[RTC_DOM];
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tm->tm_mon = (nvr->regs[RTC_MONTH] - 1);
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tm->tm_year = nvr->regs[RTC_YEAR];
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if (local->cent != 0xFF)
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tm->tm_year += (nvr->regs[local->cent] * 100) - 1900;
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} else {
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/* NVR is in BCD data mode. */
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tm->tm_sec = RTC_DCB(nvr->regs[RTC_SECONDS]);
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tm->tm_min = RTC_DCB(nvr->regs[RTC_MINUTES]);
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temp = RTC_DCB(nvr->regs[RTC_HOURS]);
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tm->tm_wday = (RTC_DCB(nvr->regs[RTC_DOW]) - 1);
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tm->tm_mday = RTC_DCB(nvr->regs[RTC_DOM]);
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tm->tm_mon = (RTC_DCB(nvr->regs[RTC_MONTH]) - 1);
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tm->tm_year = RTC_DCB(nvr->regs[RTC_YEAR]);
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if (local->cent != 0xFF)
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tm->tm_year += (RTC_DCB(nvr->regs[local->cent]) * 100) - 1900;
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}
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/* Adjust for 12/24 hour mode. */
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if (nvr->regs[RTC_REGB] & REGB_2412)
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tm->tm_hour = temp;
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else
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tm->tm_hour = ((temp & ~RTC_AMPM) % 12) + ((temp & RTC_AMPM) ? 12 : 0);
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}
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/* Set the current NVR time. */
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static void
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time_set(nvr_t *nvr, struct tm *tm)
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{
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const local_t *local = (local_t *) nvr->data;
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int year = (tm->tm_year + 1900);
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if (nvr->regs[RTC_REGB] & REGB_DM) {
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/* NVR is in Binary data mode. */
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nvr->regs[RTC_SECONDS] = tm->tm_sec;
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nvr->regs[RTC_MINUTES] = tm->tm_min;
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nvr->regs[RTC_DOW] = (tm->tm_wday + 1);
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nvr->regs[RTC_DOM] = tm->tm_mday;
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nvr->regs[RTC_MONTH] = (tm->tm_mon + 1);
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nvr->regs[RTC_YEAR] = (year % 100);
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if (local->cent != 0xFF)
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nvr->regs[local->cent] = (year / 100);
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if (nvr->regs[RTC_REGB] & REGB_2412) {
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/* NVR is in 24h mode. */
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nvr->regs[RTC_HOURS] = tm->tm_hour;
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} else {
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/* NVR is in 12h mode. */
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nvr->regs[RTC_HOURS] = (tm->tm_hour % 12) ? (tm->tm_hour % 12) : 12;
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if (tm->tm_hour > 11)
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nvr->regs[RTC_HOURS] |= RTC_AMPM;
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}
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} else {
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/* NVR is in BCD data mode. */
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nvr->regs[RTC_SECONDS] = RTC_BCD(tm->tm_sec);
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nvr->regs[RTC_MINUTES] = RTC_BCD(tm->tm_min);
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nvr->regs[RTC_DOW] = RTC_BCD(tm->tm_wday + 1);
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nvr->regs[RTC_DOM] = RTC_BCD(tm->tm_mday);
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nvr->regs[RTC_MONTH] = RTC_BCD(tm->tm_mon + 1);
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nvr->regs[RTC_YEAR] = RTC_BCD(year % 100);
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if (local->cent != 0xFF)
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nvr->regs[local->cent] = RTC_BCD(year / 100);
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if (nvr->regs[RTC_REGB] & REGB_2412) {
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/* NVR is in 24h mode. */
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nvr->regs[RTC_HOURS] = RTC_BCD(tm->tm_hour);
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} else {
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/* NVR is in 12h mode. */
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nvr->regs[RTC_HOURS] = (tm->tm_hour % 12)
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? RTC_BCD(tm->tm_hour % 12)
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: RTC_BCD(12);
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if (tm->tm_hour > 11)
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nvr->regs[RTC_HOURS] |= RTC_AMPM;
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}
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}
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}
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/* Check if the current time matches a set alarm time. */
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static int8_t
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check_alarm(nvr_t *nvr, int8_t addr)
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{
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return ((nvr->regs[addr + 1] == nvr->regs[addr]) || ((nvr->regs[addr + 1] & AL_DONTCARE) == AL_DONTCARE));
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}
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/* Check for VIA stuff. */
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static int8_t
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check_alarm_via(nvr_t *nvr, int8_t addr, int8_t addr_2)
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{
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const local_t *local = (local_t *) nvr->data;
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|
if (local->cent == RTC_CENTURY_VIA) {
|
|
return ((nvr->regs[addr_2] == nvr->regs[addr]) || ((nvr->regs[addr_2] & AL_DONTCARE) == AL_DONTCARE));
|
|
} else
|
|
return 1;
|
|
}
|
|
|
|
static void
|
|
timer_update_irq(nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
uint8_t irq = (nvr->regs[RTC_REGB] & nvr->regs[RTC_REGC]) & (REGB_UIE | REGB_AIE | REGB_PIE);
|
|
|
|
if (irq || (local->irq_state != !!irq)) {
|
|
if (irq) {
|
|
nvr->regs[RTC_REGC] |= REGC_IRQF;
|
|
picintlevel(1 << nvr->irq, &local->irq_state);
|
|
if (local->smi_enable) {
|
|
smi_raise();
|
|
local->smi_status = 1;
|
|
}
|
|
} else {
|
|
nvr->regs[RTC_REGC] &= ~REGC_IRQF;
|
|
picintclevel(1 << nvr->irq, &local->irq_state);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the NVR registers from the internal clock. */
|
|
static void
|
|
timer_update(void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
struct tm tm;
|
|
|
|
if (local->ecount == (244ULL * TIMER_USEC)) {
|
|
rtc_tick();
|
|
|
|
/* Get the current time from the internal clock. */
|
|
nvr_time_get(&tm);
|
|
|
|
/* Update registers with current time. */
|
|
time_set(nvr, &tm);
|
|
|
|
/* Check for any alarms we need to handle. */
|
|
if (check_alarm(nvr, RTC_SECONDS) && check_alarm(nvr, RTC_MINUTES) && check_alarm(nvr, RTC_HOURS) &&
|
|
check_alarm_via(nvr, RTC_DOM, RTC_ALDAY) && check_alarm_via(nvr, RTC_MONTH, RTC_ALMONTH) /* &&
|
|
check_alarm_via(nvr, RTC_DOM, RTC_ALDAY_SIS) && check_alarm_via(nvr, RTC_MONTH, RTC_ALMONT_SIS) */) {
|
|
nvr->regs[RTC_REGC] |= REGC_AF;
|
|
timer_update_irq(nvr);
|
|
}
|
|
|
|
/* Schedule the end of the update. */
|
|
local->ecount = 1984ULL * TIMER_USEC;
|
|
timer_set_delay_u64(&local->update_timer, local->ecount);
|
|
} else {
|
|
/*
|
|
* The flag and interrupt should be issued
|
|
* on update ended, not started.
|
|
*/
|
|
nvr->regs[RTC_REGC] |= REGC_UF;
|
|
timer_update_irq(nvr);
|
|
|
|
/* Clear update status. */
|
|
local->stat = 0x00;
|
|
|
|
local->ecount = 0LL;
|
|
}
|
|
}
|
|
|
|
static void
|
|
timer_load_count(nvr_t *nvr)
|
|
{
|
|
int c = nvr->regs[RTC_REGA] & REGA_RS;
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
timer_disable(&local->rtc_timer);
|
|
|
|
if ((nvr->regs[RTC_REGA] & 0x70) != 0x20) {
|
|
local->state = 0;
|
|
return;
|
|
}
|
|
|
|
local->state = 1;
|
|
|
|
switch (c) {
|
|
case 0:
|
|
local->state = 0;
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
local->count = 1 << (c + 6);
|
|
timer_set_delay_u64(&local->rtc_timer, (local->count) * RTCCONST);
|
|
break;
|
|
default:
|
|
local->count = 1 << (c - 1);
|
|
timer_set_delay_u64(&local->rtc_timer, (local->count) * RTCCONST);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
timer_intr(void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
const local_t *local = (local_t *) nvr->data;
|
|
|
|
if (local->state == 1) {
|
|
timer_load_count(nvr);
|
|
|
|
nvr->regs[RTC_REGC] |= REGC_PF;
|
|
timer_update_irq(nvr);
|
|
}
|
|
}
|
|
|
|
/* Callback from internal clock, another second passed. */
|
|
static void
|
|
timer_tick(nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
/* Only update it there is no SET in progress.
|
|
Also avoid updating it is DV2-DV0 are not set to 0, 1, 0. */
|
|
if (((nvr->regs[RTC_REGA] & 0x70) == 0x20) && !(nvr->regs[RTC_REGB] & REGB_SET)) {
|
|
/* Set the UIP bit, announcing the update. */
|
|
local->stat = REGA_UIP;
|
|
|
|
/* Schedule the actual update. */
|
|
local->ecount = 244ULL * TIMER_USEC;
|
|
timer_set_delay_u64(&local->update_timer, local->ecount);
|
|
}
|
|
}
|
|
|
|
static void
|
|
nvr_reg_common_write(uint16_t reg, uint8_t val, nvr_t *nvr, local_t *local)
|
|
{
|
|
if (local->lock[reg])
|
|
return;
|
|
if ((reg == 0x2c) && (local->flags & FLAG_AMI_1994_HACK))
|
|
nvr->is_new = 0;
|
|
if ((reg == 0x2d) && (local->flags & FLAG_AMI_1992_HACK))
|
|
nvr->is_new = 0;
|
|
if ((reg == 0x52) && (local->flags & FLAG_AMI_1995_HACK))
|
|
nvr->is_new = 0;
|
|
if ((reg >= 0x38) && (reg <= 0x3f) && local->wp[0])
|
|
return;
|
|
if ((reg >= 0xb8) && (reg <= 0xbf) && local->wp[1])
|
|
return;
|
|
if (nvr->regs[reg] != val) {
|
|
nvr->regs[reg] = val;
|
|
if ((reg >= 0x0d) && ((local->cent == 0xff) || (reg != local->cent)))
|
|
nvr_dosave = 1;
|
|
}
|
|
}
|
|
|
|
/* This must be exposed because ACPI uses it. */
|
|
void
|
|
nvr_reg_write(uint16_t reg, uint8_t val, void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
struct tm tm;
|
|
uint8_t old;
|
|
|
|
old = nvr->regs[reg];
|
|
switch (reg) {
|
|
case RTC_SECONDS: /* bit 7 of seconds is read-only */
|
|
nvr_reg_common_write(reg, val & 0x7f, nvr, local);
|
|
break;
|
|
|
|
case RTC_REGA:
|
|
if ((val & nvr->regs[RTC_REGA]) & ~REGA_UIP) {
|
|
nvr->regs[RTC_REGA] = (nvr->regs[RTC_REGA] & REGA_UIP) | (val & ~REGA_UIP);
|
|
timer_load_count(nvr);
|
|
}
|
|
break;
|
|
|
|
case RTC_REGB:
|
|
if (((old ^ val) & REGB_SET) && (val & REGB_SET)) {
|
|
/* According to the datasheet... */
|
|
val &= ~REGB_UIE;
|
|
local->stat &= ~REGA_UIP;
|
|
}
|
|
|
|
nvr->regs[RTC_REGB] = val;
|
|
timer_update_irq(nvr);
|
|
break;
|
|
|
|
case RTC_REGC: /* R/O */
|
|
break;
|
|
|
|
case RTC_REGD: /* R/O */
|
|
/* This is needed for VIA, where writing to this register changes a write-only
|
|
bit whose value is read from power management register 42. */
|
|
nvr->regs[RTC_REGD] = val & 0x80;
|
|
break;
|
|
|
|
case 0x32:
|
|
if ((reg == 0x32) && (local->cent == RTC_CENTURY_VIA) && local->wp_32)
|
|
break;
|
|
nvr_reg_common_write(reg, val, nvr, local);
|
|
break;
|
|
|
|
default: /* non-RTC registers are just NVRAM */
|
|
nvr_reg_common_write(reg, val, nvr, local);
|
|
break;
|
|
}
|
|
|
|
if ((reg < RTC_REGA) || ((local->cent != 0xff) && (reg == local->cent))) {
|
|
if ((reg != 1) && (reg != 3) && (reg != 5)) {
|
|
if ((old != val) && !(time_sync & TIME_SYNC_ENABLED)) {
|
|
/* Update internal clock. */
|
|
time_get(nvr, &tm);
|
|
nvr_time_set(&tm);
|
|
// nvr_dosave = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write to one of the NVR registers. */
|
|
static void
|
|
nvr_write(uint16_t addr, uint8_t val, void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
uint8_t addr_id = (addr & 0x0e) >> 1;
|
|
|
|
cycles -= ISA_CYCLES(8);
|
|
|
|
if (local->bank[addr_id] == 0xff)
|
|
return;
|
|
|
|
if (addr & 1) {
|
|
#if 0
|
|
if (local->bank[addr_id] == 0xff)
|
|
return;
|
|
#endif
|
|
nvr_reg_write(local->addr[addr_id], val, priv);
|
|
} else {
|
|
local->addr[addr_id] = (val & (nvr->size - 1));
|
|
/* Some chipsets use a 256 byte NVRAM but ports 70h and 71h always access only 128 bytes. */
|
|
if (addr_id == 0x0) {
|
|
local->addr[addr_id] &= 0x7f;
|
|
/* Needed for OPTi 82C601/82C602 and NSC PC87306. */
|
|
if (local->flags & FLAG_MULTI_BANK)
|
|
local->addr[addr_id] |= (0x80 * local->bank[addr_id]);
|
|
} else if ((addr_id == 0x1) && (local->flags & FLAG_PIIX4))
|
|
local->addr[addr_id] = (local->addr[addr_id] & 0x7f) | 0x80;
|
|
if (local->bank[addr_id] > 0)
|
|
local->addr[addr_id] = (local->addr[addr_id] & 0x7f) | (0x80 * local->bank[addr_id]);
|
|
if (!(local->flags & FLAG_NO_NMI))
|
|
nmi_mask = (~val & 0x80);
|
|
}
|
|
}
|
|
|
|
/* Get the NVR register index (used for APC). */
|
|
uint8_t
|
|
nvr_get_index(void *priv, uint8_t addr_id)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
uint8_t ret;
|
|
|
|
ret = local->addr[addr_id];
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Read from one of the NVR registers. */
|
|
static uint8_t
|
|
nvr_read(uint16_t addr, void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
const local_t *local = (local_t *) nvr->data;
|
|
uint8_t ret = 0xff;
|
|
uint8_t addr_id = (addr & 0x0e) >> 1;
|
|
uint16_t i;
|
|
uint16_t checksum = 0x0000;
|
|
|
|
cycles -= ISA_CYCLES(8);
|
|
|
|
if (local->bank[addr_id] == 0xff)
|
|
ret = 0xff;
|
|
else if (addr & 1)
|
|
switch (local->addr[addr_id]) {
|
|
case RTC_REGA:
|
|
ret = (nvr->regs[RTC_REGA] & 0x7f) | local->stat;
|
|
break;
|
|
|
|
case RTC_REGC:
|
|
ret = nvr->regs[RTC_REGC] & (REGC_IRQF | REGC_PF | REGC_AF | REGC_UF);
|
|
nvr->regs[RTC_REGC] &= ~(REGC_IRQF | REGC_PF | REGC_AF | REGC_UF);
|
|
timer_update_irq(nvr);
|
|
break;
|
|
|
|
case RTC_REGD:
|
|
/* Bits 6-0 of this register always read 0. Bit 7 is battery state,
|
|
we should always return it set, as that means the battery is OK. */
|
|
ret = REGD_VRT;
|
|
break;
|
|
|
|
case 0x11:
|
|
if (local->flags & FLAG_MARTIN_HACK)
|
|
ret = nvr->regs[local->addr[addr_id]] | 0x02;
|
|
else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x2c:
|
|
if (!nvr->is_new && (local->flags & FLAG_AMI_1994_HACK))
|
|
ret = nvr->regs[local->addr[addr_id]] & 0x7f;
|
|
else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x2d:
|
|
if (!nvr->is_new && (local->flags & FLAG_AMI_1992_HACK))
|
|
ret = nvr->regs[local->addr[addr_id]] & 0xf7;
|
|
else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x2e:
|
|
case 0x2f:
|
|
if (!nvr->is_new && (local->flags & FLAG_AMI_1992_HACK)) {
|
|
for (i = 0x10; i <= 0x2d; i++) {
|
|
if (i == 0x2d)
|
|
checksum += (nvr->regs[i] & 0xf7);
|
|
else
|
|
checksum += nvr->regs[i];
|
|
}
|
|
if (local->addr[addr_id] == 0x2e)
|
|
ret = checksum >> 8;
|
|
else
|
|
ret = checksum & 0xff;
|
|
} else if (!nvr->is_new && (local->flags & FLAG_AMI_1994_HACK)) {
|
|
for (i = 0x10; i <= 0x2d; i++) {
|
|
if (i == 0x2c)
|
|
checksum += (nvr->regs[i] & 0x7f);
|
|
else
|
|
checksum += nvr->regs[i];
|
|
}
|
|
if (local->addr[addr_id] == 0x2e)
|
|
ret = checksum >> 8;
|
|
else
|
|
ret = checksum & 0xff;
|
|
} else if (!nvr->is_new && (local->flags & FLAG_MARTIN_HACK)) {
|
|
for (i = 0x10; i <= 0x2d; i++) {
|
|
if (i == 0x11)
|
|
checksum += (nvr->regs[i] | 0x02);
|
|
else
|
|
checksum += nvr->regs[i];
|
|
}
|
|
if (local->addr[addr_id] == 0x2e)
|
|
ret = checksum >> 8;
|
|
else
|
|
ret = checksum & 0xff;
|
|
} else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x3e:
|
|
case 0x3f:
|
|
if (!nvr->is_new && (local->flags & FLAG_AMI_1995_HACK)) {
|
|
/* The checksum at 3E-3F is for 37-3D and 40-7F. */
|
|
for (i = 0x37; i <= 0x3d; i++)
|
|
checksum += nvr->regs[i];
|
|
for (i = 0x40; i <= 0x7f; i++) {
|
|
if (i == 0x52)
|
|
checksum += (nvr->regs[i] & 0xf3);
|
|
else
|
|
checksum += nvr->regs[i];
|
|
}
|
|
if (local->addr[addr_id] == 0x3e)
|
|
ret = checksum >> 8;
|
|
else
|
|
ret = checksum & 0xff;
|
|
} else if (!nvr->is_new && (local->flags & FLAG_P6RP4_HACK)) {
|
|
/* The checksum at 3E-3F is for 37-3D and 40-51. */
|
|
for (i = 0x37; i <= 0x3d; i++)
|
|
checksum += nvr->regs[i];
|
|
for (i = 0x40; i <= 0x51; i++) {
|
|
if (i == 0x43)
|
|
checksum += (nvr->regs[i] | 0x02);
|
|
else
|
|
checksum += nvr->regs[i];
|
|
}
|
|
if (local->addr[addr_id] == 0x3e)
|
|
ret = checksum >> 8;
|
|
else
|
|
ret = checksum & 0xff;
|
|
} else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x43:
|
|
if (!nvr->is_new && (local->flags & FLAG_P6RP4_HACK))
|
|
ret = nvr->regs[local->addr[addr_id]] | 0x02;
|
|
else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
case 0x52:
|
|
if (!nvr->is_new && (local->flags & FLAG_AMI_1995_HACK))
|
|
ret = nvr->regs[local->addr[addr_id]] & 0xf3;
|
|
else
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
|
|
default:
|
|
if (!(local->lock[local->addr[addr_id]] & 0x02))
|
|
ret = nvr->regs[local->addr[addr_id]];
|
|
break;
|
|
}
|
|
else {
|
|
ret = local->addr[addr_id];
|
|
if (!local->read_addr)
|
|
ret &= 0x80;
|
|
if (alt_access)
|
|
ret = (ret & 0x7f) | (nmi_mask ? 0x00 : 0x80);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Secondary NVR write - used by SMC. */
|
|
static void
|
|
nvr_sec_write(uint16_t addr, uint8_t val, void *priv)
|
|
{
|
|
nvr_write(0x72 + (addr & 1), val, priv);
|
|
}
|
|
|
|
/* Secondary NVR read - used by SMC. */
|
|
static uint8_t
|
|
nvr_sec_read(uint16_t addr, void *priv)
|
|
{
|
|
return nvr_read(0x72 + (addr & 1), priv);
|
|
}
|
|
|
|
/* Reset the RTC state to 1980/01/01 00:00. */
|
|
static void
|
|
nvr_reset(nvr_t *nvr)
|
|
{
|
|
const local_t *local = (local_t *) nvr->data;
|
|
|
|
#if 0
|
|
memset(nvr->regs, local->def, RTC_REGS);
|
|
#endif
|
|
memset(nvr->regs, local->def, nvr->size);
|
|
nvr->regs[RTC_DOM] = 1;
|
|
nvr->regs[RTC_MONTH] = 1;
|
|
nvr->regs[RTC_YEAR] = RTC_BCD(80);
|
|
if (local->cent != 0xFF)
|
|
nvr->regs[local->cent] = RTC_BCD(19);
|
|
|
|
nvr->regs[RTC_REGD] = REGD_VRT;
|
|
}
|
|
|
|
/* Process after loading from file. */
|
|
static void
|
|
nvr_start(nvr_t *nvr)
|
|
{
|
|
const local_t *local = (local_t *) nvr->data;
|
|
|
|
struct tm tm;
|
|
int default_found = 0;
|
|
|
|
for (uint16_t i = 0; i < nvr->size; i++) {
|
|
if (nvr->regs[i] == local->def)
|
|
default_found++;
|
|
}
|
|
|
|
if (default_found == nvr->size)
|
|
nvr->regs[0x0e] = 0xff; /* If load failed or it loaded an uninitialized NVR,
|
|
mark everything as bad. */
|
|
|
|
/* Initialize the internal and chip times. */
|
|
if (time_sync & TIME_SYNC_ENABLED) {
|
|
/* Use the internal clock's time. */
|
|
nvr_time_get(&tm);
|
|
time_set(nvr, &tm);
|
|
} else {
|
|
/* Set the internal clock from the chip time. */
|
|
time_get(nvr, &tm);
|
|
nvr_time_set(&tm);
|
|
}
|
|
|
|
/* Start the RTC. */
|
|
nvr->regs[RTC_REGA] = (REGA_RS2 | REGA_RS1);
|
|
nvr->regs[RTC_REGB] = REGB_2412;
|
|
}
|
|
|
|
static void
|
|
nvr_at_speed_changed(void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
timer_load_count(nvr);
|
|
|
|
timer_disable(&local->update_timer);
|
|
if (local->ecount > 0ULL)
|
|
timer_set_delay_u64(&local->update_timer, local->ecount);
|
|
|
|
timer_disable(&nvr->onesec_time);
|
|
timer_set_delay_u64(&nvr->onesec_time, (10000ULL * TIMER_USEC));
|
|
}
|
|
|
|
void
|
|
nvr_at_handler(int set, uint16_t base, nvr_t *nvr)
|
|
{
|
|
io_handler(set, base, 2,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
}
|
|
|
|
void
|
|
nvr_at_index_read_handler(int set, uint16_t base, nvr_t *nvr)
|
|
{
|
|
io_handler(0, base, 1,
|
|
NULL, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
nvr_at_handler(0, base, nvr);
|
|
|
|
if (set)
|
|
nvr_at_handler(1, base, nvr);
|
|
else {
|
|
io_handler(1, base, 1,
|
|
NULL, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
io_handler(1, base + 1, 1,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
}
|
|
}
|
|
|
|
void
|
|
nvr_at_data_port(int set, nvr_t *nvr)
|
|
{
|
|
io_handler(0, 0x71, 1,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
|
|
if (set)
|
|
io_handler(1, 0x71, 1,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
}
|
|
|
|
void
|
|
nvr_at_sec_handler(int set, uint16_t base, nvr_t *nvr)
|
|
{
|
|
io_handler(set, base, 2,
|
|
nvr_sec_read, NULL, NULL, nvr_sec_write, NULL, NULL, nvr);
|
|
}
|
|
|
|
void
|
|
nvr_read_addr_set(int set, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
local->read_addr = set;
|
|
}
|
|
|
|
void
|
|
nvr_wp_set(int set, int h, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
local->wp[h] = set;
|
|
}
|
|
|
|
void
|
|
nvr_via_wp_set(int set, int reg, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
if (reg == 0x0d)
|
|
local->wp_0d = set;
|
|
else
|
|
local->wp_32 = set;
|
|
}
|
|
|
|
void
|
|
nvr_bank_set(int base, uint8_t bank, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
local->bank[base] = bank;
|
|
}
|
|
|
|
void
|
|
nvr_lock_set(int base, int size, int lock, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
for (int i = 0; i < size; i++)
|
|
local->lock[base + i] = lock;
|
|
}
|
|
|
|
void
|
|
nvr_irq_set(int irq, nvr_t *nvr)
|
|
{
|
|
nvr->irq = irq;
|
|
}
|
|
|
|
void
|
|
nvr_smi_enable(int enable, nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
local->smi_enable = enable;
|
|
|
|
if (!enable)
|
|
local->smi_status = 0;
|
|
}
|
|
|
|
uint8_t
|
|
nvr_smi_status(nvr_t *nvr)
|
|
{
|
|
const local_t *local = (local_t *) nvr->data;
|
|
|
|
return local->smi_status;
|
|
}
|
|
|
|
void
|
|
nvr_smi_status_clear(nvr_t *nvr)
|
|
{
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
local->smi_status = 0;
|
|
}
|
|
|
|
static void
|
|
nvr_at_reset(void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
|
|
/* These bits are reset on reset. */
|
|
nvr->regs[RTC_REGB] &= ~(REGB_PIE | REGB_AIE | REGB_UIE | REGB_SQWE);
|
|
nvr->regs[RTC_REGC] &= ~(REGC_PF | REGC_AF | REGC_UF | REGC_IRQF);
|
|
}
|
|
|
|
static void *
|
|
nvr_at_init(const device_t *info)
|
|
{
|
|
local_t *local;
|
|
nvr_t *nvr;
|
|
|
|
/* Allocate an NVR for this machine. */
|
|
nvr = (nvr_t *) malloc(sizeof(nvr_t));
|
|
if (nvr == NULL)
|
|
return (NULL);
|
|
memset(nvr, 0x00, sizeof(nvr_t));
|
|
|
|
local = (local_t *) malloc(sizeof(local_t));
|
|
memset(local, 0x00, sizeof(local_t));
|
|
nvr->data = local;
|
|
|
|
/* This is machine specific. */
|
|
nvr->size = machines[machine].nvrmask + 1;
|
|
local->lock = (uint8_t *) malloc(nvr->size);
|
|
memset(local->lock, 0x00, nvr->size);
|
|
local->def = 0xff /*0x00*/;
|
|
local->flags = 0x00;
|
|
switch (info->local & 0x0f) {
|
|
case 0: /* standard AT, no century register */
|
|
if (info->local == 32) {
|
|
local->flags |= FLAG_P6RP4_HACK;
|
|
nvr->irq = 8;
|
|
local->cent = RTC_CENTURY_AT;
|
|
} else {
|
|
nvr->irq = 8;
|
|
local->cent = 0xff;
|
|
}
|
|
break;
|
|
|
|
case 1: /* standard AT */
|
|
case 5: /* AMI WinBIOS 1994 */
|
|
case 6: /* AMI BIOS 1995 */
|
|
if ((info->local & 0x1f) == 0x11) {
|
|
local->flags |= FLAG_PIIX4;
|
|
local->def = 0x00;
|
|
} else {
|
|
local->def = 0x00;
|
|
if ((info->local & 0x1f) == 0x15)
|
|
local->flags |= FLAG_AMI_1994_HACK;
|
|
else if ((info->local & 0x1f) == 0x16)
|
|
local->flags |= FLAG_AMI_1995_HACK;
|
|
else
|
|
local->def = 0xff;
|
|
}
|
|
nvr->irq = 8;
|
|
local->cent = RTC_CENTURY_AT;
|
|
break;
|
|
|
|
case 2: /* PS/1 or PS/2 */
|
|
nvr->irq = 8;
|
|
local->cent = RTC_CENTURY_PS;
|
|
local->def = 0x00;
|
|
if (info->local & 0x10)
|
|
local->flags |= FLAG_NO_NMI;
|
|
break;
|
|
|
|
case 3: /* Amstrad PC's */
|
|
nvr->irq = 1;
|
|
local->cent = RTC_CENTURY_AT;
|
|
local->def = 0xff;
|
|
if (info->local & 0x10)
|
|
local->flags |= FLAG_NO_NMI;
|
|
break;
|
|
|
|
case 4: /* IBM AT */
|
|
if (info->local & 0x10) {
|
|
local->def = 0x00;
|
|
local->flags |= FLAG_AMI_1992_HACK;
|
|
} else if ((info->local == 36) || (info->local == 68)) {
|
|
local->def = 0x00;
|
|
if (info->local == 68)
|
|
local->flags |= FLAG_MARTIN_HACK;
|
|
} else
|
|
local->def = 0xff;
|
|
nvr->irq = 8;
|
|
local->cent = RTC_CENTURY_AT;
|
|
break;
|
|
|
|
case 7: /* VIA VT82C586B */
|
|
nvr->irq = 8;
|
|
local->cent = RTC_CENTURY_VIA;
|
|
break;
|
|
case 8: /* Epson Equity LT */
|
|
nvr->irq = -1;
|
|
local->cent = RTC_CENTURY_ELT;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (info->local & 0x20)
|
|
local->def = 0x00;
|
|
|
|
if (info->local & 0x40)
|
|
local->flags |= FLAG_MULTI_BANK;
|
|
|
|
local->read_addr = 1;
|
|
|
|
/* Set up any local handlers here. */
|
|
nvr->reset = nvr_reset;
|
|
nvr->start = nvr_start;
|
|
nvr->tick = timer_tick;
|
|
|
|
/* Initialize the generic NVR. */
|
|
nvr_init(nvr);
|
|
|
|
if (nvr->is_new && (local->flags & FLAG_MARTIN_HACK))
|
|
nvr->regs[0x11] = nvr->regs[0x2f] = 0x02;
|
|
|
|
if (nvr_at_inited == 0) {
|
|
/* Start the timers. */
|
|
timer_add(&local->update_timer, timer_update, nvr, 0);
|
|
|
|
timer_add(&local->rtc_timer, timer_intr, nvr, 0);
|
|
/* On power on, if the oscillator is disabled, it's reenabled. */
|
|
if ((nvr->regs[RTC_REGA] & 0x70) == 0x00)
|
|
nvr->regs[RTC_REGA] = (nvr->regs[RTC_REGA] & 0x8f) | 0x20;
|
|
nvr_at_reset(nvr);
|
|
timer_load_count(nvr);
|
|
|
|
/* Set up the I/O handler for this device. */
|
|
if (info->local == 8) {
|
|
io_sethandler(0x11b4, 2,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
} else {
|
|
io_sethandler(0x0070, 2,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
}
|
|
if (((info->local & 0x1f) == 0x11) || ((info->local & 0x1f) == 0x17)) {
|
|
io_sethandler(0x0072, 2,
|
|
nvr_read, NULL, NULL, nvr_write, NULL, NULL, nvr);
|
|
}
|
|
|
|
nvr_at_inited = 1;
|
|
}
|
|
|
|
/* This is a hack but it is required for the machine to boot properly, no idea why. */
|
|
if (nvr->is_new && !strcmp(machine_get_internal_name(), "spitfire"))
|
|
nvr->regs[0x33] = nvr->regs[0x34] = 0xff;
|
|
|
|
return nvr;
|
|
}
|
|
|
|
static void
|
|
nvr_at_close(void *priv)
|
|
{
|
|
nvr_t *nvr = (nvr_t *) priv;
|
|
local_t *local = (local_t *) nvr->data;
|
|
|
|
nvr_close();
|
|
|
|
timer_disable(&local->rtc_timer);
|
|
timer_disable(&local->update_timer);
|
|
timer_disable(&nvr->onesec_time);
|
|
|
|
if (nvr != NULL) {
|
|
if (nvr->fn != NULL)
|
|
free(nvr->fn);
|
|
|
|
if (nvr->data != NULL)
|
|
free(nvr->data);
|
|
|
|
free(nvr);
|
|
}
|
|
|
|
if (nvr_at_inited == 1)
|
|
nvr_at_inited = 0;
|
|
}
|
|
|
|
const device_t at_nvr_old_device = {
|
|
.name = "PC/AT NVRAM (No century)",
|
|
.internal_name = "at_nvr_old",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t at_nvr_device = {
|
|
.name = "PC/AT NVRAM",
|
|
.internal_name = "at_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 1,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t at_mb_nvr_device = {
|
|
.name = "PC/AT NVRAM",
|
|
.internal_name = "at_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x40 | 0x20 | 1,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ps_nvr_device = {
|
|
.name = "PS/1 or PS/2 NVRAM",
|
|
.internal_name = "ps_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 2,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t amstrad_nvr_device = {
|
|
.name = "Amstrad NVRAM",
|
|
.internal_name = "amstrad_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 3,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ibmat_nvr_device = {
|
|
.name = "IBM AT NVRAM",
|
|
.internal_name = "ibmat_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 4,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t piix4_nvr_device = {
|
|
.name = "Intel PIIX4 PC/AT NVRAM",
|
|
.internal_name = "piix4_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 1,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ps_no_nmi_nvr_device = {
|
|
.name = "PS/1 or PS/2 NVRAM (No NMI)",
|
|
.internal_name = "ps1_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 2,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t amstrad_no_nmi_nvr_device = {
|
|
.name = "Amstrad NVRAM (No NMI)",
|
|
.internal_name = "amstrad_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 3,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ami_1992_nvr_device = {
|
|
.name = "AMI Color 1992 PC/AT NVRAM",
|
|
.internal_name = "ami_1992_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 4,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ami_1994_nvr_device = {
|
|
.name = "AMI WinBIOS 1994 PC/AT NVRAM",
|
|
.internal_name = "ami_1994_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 5,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t ami_1995_nvr_device = {
|
|
.name = "AMI WinBIOS 1995 PC/AT NVRAM",
|
|
.internal_name = "ami_1995_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 6,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t via_nvr_device = {
|
|
.name = "VIA PC/AT NVRAM",
|
|
.internal_name = "via_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 0x10 | 7,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t p6rp4_nvr_device = {
|
|
.name = "ASUS P/I-P6RP4 PC/AT NVRAM",
|
|
.internal_name = "p6rp4_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 32,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t amstrad_megapc_nvr_device = {
|
|
.name = "Amstrad MegaPC NVRAM",
|
|
.internal_name = "amstrad_megapc_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 36,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t martin_nvr_device = {
|
|
.name = "Zeos Martin NVRAM",
|
|
.internal_name = "martin_nvr",
|
|
.flags = DEVICE_ISA16,
|
|
.local = 68,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t elt_nvr_device = {
|
|
.name = "Epson Equity LT NVRAM",
|
|
.internal_name = "elt_nvr",
|
|
.flags = DEVICE_ISA,
|
|
.local = 8,
|
|
.init = nvr_at_init,
|
|
.close = nvr_at_close,
|
|
.reset = nvr_at_reset,
|
|
.available = NULL,
|
|
.speed_changed = nvr_at_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|