abf009e541
Moved CD-ROM read data buffer declaration and definitions to SCSI source files and headers, but still applying to IDE when needed. SCSI Read commands now return the correct sectors on callback. DMA bug fixes.
614 lines
15 KiB
C
614 lines
15 KiB
C
/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include "ibm.h"
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#include "disc.h"
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#include "dma.h"
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#include "fdc.h"
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#include "io.h"
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#include "mem.h"
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#include "video.h"
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static uint8_t dmaregs[16];
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static int dmaon[4];
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static uint8_t dma16regs[16];
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static int dma16on[4];
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static uint8_t dmapages[16];
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void dma_reset()
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{
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int c;
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dma.wp = 0;
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for (c = 0; c < 16; c++)
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dmaregs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma.mode[c] = 0;
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dma.ac[c] = 0;
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dma.cc[c] = 0;
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dma.ab[c] = 0;
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dma.cb[c] = 0;
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}
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dma.m = 0;
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dma16.wp = 0;
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for (c = 0; c < 16; c++)
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dma16regs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma16.mode[c] = 0;
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dma16.ac[c] = 0;
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dma16.cc[c] = 0;
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dma16.ab[c] = 0;
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dma16.cb[c] = 0;
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}
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dma16.m = 0;
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}
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uint8_t dma_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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// printf("Read DMA %04X %04X:%04X %i %02X\n",addr,CS,pc, pic_intpending, pic.pend);
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp)
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return dma.ac[(addr >> 1) & 3] & 0xff;
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return dma.ac[(addr >> 1) & 3] >> 8;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) temp = dma.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma.stat;
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dma.stat = 0;
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return temp;
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case 0xd:
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return 0;
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}
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// printf("Bad DMA read %04X %04X:%04X\n",addr,CS,pc);
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return dmaregs[addr & 0xf];
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}
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void dma_write(uint16_t addr, uint8_t val, void *priv)
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{
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// printf("Write DMA %04X %02X %04X:%04X\n",addr,val,CS,pc);
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dmaregs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
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else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma.ac[(addr >> 1) & 3] = dma.ab[(addr >> 1) & 3] & 0xffff;
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dmaon[(addr >> 1) & 3] = 1;
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma.cc[(addr >> 1) & 3] = dma.cb[(addr >> 1) & 3] & 0xffff;
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// pclog("DMA count for channel %i now: %02X\n", (addr >> 1) & 3, dma.cc[(addr >> 1) & 3]);
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dmaon[(addr >> 1) & 3] = 1;
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return;
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case 8: /*Control register*/
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dma.command = val;
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma.m |= (1 << (val & 3));
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else dma.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma.mode[val & 3] = val;
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return;
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case 0xc: /*Clear FF*/
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dma.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma.wp = 0;
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dma.stat = 0;
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dma.m = 0xf;
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return;
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case 0xe: /*Mask reset*/
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dma.m = 0;
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return;
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case 0xf: /*Mask write*/
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dma.m = val & 0xf;
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return;
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}
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}
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uint8_t dma16_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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// printf("Read DMA %04X %04X:%04X\n",addr,cs>>4,pc);
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addr >>= 1;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma16.wp)
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return dma16.ac[(addr >> 1) & 3] & 0xff;
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return dma16.ac[(addr >> 1) & 3] >> 8;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) temp = dma16.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma16.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma16.stat;
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dma16.stat = 0;
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return temp;
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}
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return dma16regs[addr & 0xf];
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}
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void dma16_write(uint16_t addr, uint8_t val, void *priv)
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{
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// printf("Write dma16 %04X %02X %04X:%04X\n",addr,val,CS,pc);
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addr >>= 1;
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dma16regs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
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else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma16.ac[(addr >> 1) & 3] = dma16.ab[(addr >> 1) & 3] & 0xffff;
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dma16on[(addr >> 1) & 3] = 1;
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma16.cc[(addr >> 1) & 3] = dma16.cb[(addr >> 1) & 3] & 0xffff;
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dma16on[(addr >> 1) & 3] = 1;
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return;
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case 8: /*Control register*/
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma16.m |= (1 << (val & 3));
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else dma16.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma16.mode[val & 3] = val;
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return;
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case 0xc: /*Clear FF*/
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dma16.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma16.wp = 0;
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dma16.stat = 0;
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dma16.m = 0xf;
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return;
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case 0xe: /*Mask reset*/
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dma16.m = 0;
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return;
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case 0xf: /*Mask write*/
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dma16.m = val&0xf;
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return;
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}
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}
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void dma_page_write(uint16_t addr, uint8_t val, void *priv)
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{
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dmapages[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 1:
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dma.page[2] = (AT) ? val : val & 0xf;
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break;
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case 2:
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dma.page[3] = (AT) ? val : val & 0xf;
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break;
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case 3:
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dma.page[1] = (AT) ? val : val & 0xf;
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break;
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case 0x7:
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if (is386)
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{
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dma.page[0] = (AT) ? val : val & 0xf;
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}
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break;
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case 0x9:
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dma16.page[2] = val;
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break;
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case 0xa:
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dma16.page[3] = val;
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break;
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case 0xb:
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dma16.page[1] = val;
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break;
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}
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}
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uint8_t dma_page_read(uint16_t addr, void *priv)
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{
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return dmapages[addr & 0xf];
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}
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void dma_init()
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{
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io_sethandler(0x0000, 0x0010, dma_read, NULL, NULL, dma_write, NULL, NULL, NULL);
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io_sethandler(0x0080, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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void dma16_init()
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{
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io_sethandler(0x00C0, 0x0020, dma16_read, NULL, NULL, dma16_write, NULL, NULL, NULL);
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io_sethandler(0x0088, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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void dma_alias_set()
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{
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io_sethandler(0x0090, 0x0010, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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void dma_alias_remove()
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{
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io_removehandler(0x0090, 0x0010, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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void dma_alias_remove_piix()
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{
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io_removehandler(0x0090, 0x0001, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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io_removehandler(0x0094, 0x0003, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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io_removehandler(0x0098, 0x0001, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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io_removehandler(0x009C, 0x0003, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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uint8_t _dma_read(uint32_t addr)
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{
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return mem_readb_phys(addr);
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}
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uint16_t _dma_readw(uint32_t addr)
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{
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return mem_readw_phys(addr);
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}
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void _dma_write(uint32_t addr, uint8_t val)
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{
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mem_writeb_phys(addr, val);
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mem_invalidate_range(addr, addr);
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}
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void _dma_writew(uint32_t addr, uint16_t val)
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{
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mem_writew_phys(addr, val);
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mem_invalidate_range(addr, addr + 1);
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}
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int dma_is_masked(int channel)
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{
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if (channel < 4)
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{
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if (dma.m & (1 << channel))
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{
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return 1;
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}
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if (AT)
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{
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if (dma16.m & 1)
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{
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return 1;
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}
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}
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}
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else
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{
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channel &= 3;
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if (dma16.m & (1 << channel))
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{
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return 1;
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}
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}
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return 0;
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}
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int dma_channel_mode(int channel)
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{
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if (channel < 4)
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{
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return (dma.mode[channel] & 0xC) >> 2;
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}
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else
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{
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channel &= 3;
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return (dma16.mode[channel] & 0xC) >> 2;
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}
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}
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DMA * get_dma_controller(int channel)
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{
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if (channel < 4)
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{
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return &dma;
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}
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else
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{
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return &dma16;
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}
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}
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int dma_channel_read(int channel)
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{
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uint16_t temp;
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int tc = 0;
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int cmode = 0;
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int real_channel = channel & 3;
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int mem_over = 0;
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DMA *dma_controller;
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cmode = dma_channel_mode(channel);
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channel &= 7;
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if ((channel >= 4) && !AT)
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{
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// pclog ("DMA read - channel is 4 or higher on a non-AT machine\n");
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return DMA_NODATA;
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}
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dma_controller = get_dma_controller(channel);
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if (dma_controller->command & 0x04)
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{
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// pclog ("DMA read - channel bit 2 of control bit is set\n");
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return DMA_NODATA;
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}
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if (!AT)
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refreshread();
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if ((channel == 4) || dma_is_masked(channel))
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{
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// pclog ("DMA read - channel is 4 or masked\n");
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return DMA_NODATA;
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}
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if (cmode)
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{
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if (cmode != 2)
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{
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// pclog ("DMA read - transfer mode (%i) is 1 or 3\n", cmode);
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return DMA_NODATA;
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}
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else
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{
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if (channel < 4)
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{
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temp = _dma_read(dma_controller->ac[real_channel] + (dma_controller->page[real_channel] << 16));
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}
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else
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{
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temp = _dma_readw((dma_controller->ac[real_channel] << 1) + ((dma_controller->page[real_channel] & ~1) << 16));
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}
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}
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}
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if (dma_controller->mode[real_channel] & 0x20)
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{
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if (dma_controller->ac[real_channel] == 0)
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{
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mem_over = 1;
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}
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dma_controller->ac[real_channel]--;
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}
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else
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{
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if (dma_controller->ac[real_channel] == 0xFFFF)
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{
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mem_over = 1;
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}
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dma_controller->ac[real_channel]++;
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}
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dma_controller->ac[real_channel] &= 0xffff;
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dma_controller->cc[real_channel]--;
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if ((dma_controller->cc[real_channel] < 0) || mem_over)
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{
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tc = 1;
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if (dma_controller->mode[real_channel] & 0x10) /*Auto-init*/
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{
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// pclog("DMA read auto-init\n");
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dma_controller->cc[real_channel] = dma_controller->cb[real_channel] & 0xffff;
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dma_controller->ac[real_channel] = dma_controller->ab[real_channel] & 0xffff;
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}
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else
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{
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dma_controller->cc[real_channel] &= 0xffff;
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dma_controller->m |= (1 << real_channel);
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}
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dma_controller->stat |= (1 << real_channel);
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}
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if (tc)
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{
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// pclog("DMA read over in transfer mode %i (value %04X)!\n", cmode, temp);
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return temp | DMA_OVER;
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}
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// pclog("DMA read success (value %04X)\n", temp);
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return temp;
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}
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int dma_channel_write(int channel, uint16_t val)
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{
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int tc = 0;
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int cmode = 0;
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int real_channel = channel & 3;
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int mem_over = 0;
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DMA *dma_controller;
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cmode = dma_channel_mode(channel);
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channel &= 7;
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if ((channel >= 4) && !AT)
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{
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// pclog ("DMA write - channel is 4 or higher on a non-AT machine\n");
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return DMA_NODATA;
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}
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dma_controller = get_dma_controller(channel);
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if (dma_controller->command & 0x04)
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{
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// pclog ("DMA write - channel bit 2 of control bit is set\n");
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return DMA_NODATA;
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}
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if (!AT)
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refreshread();
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if ((channel == 4) || dma_is_masked(channel))
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{
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// pclog ("DMA write - channel is 4 or masked\n");
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return DMA_NODATA;
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}
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if (cmode)
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{
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if (cmode != 1)
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{
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// pclog ("DMA write - transfer mode (%i) is 2 or 3\n", cmode);
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return DMA_NODATA;
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}
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if (channel < 4)
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{
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_dma_write(dma_controller->ac[real_channel] + (dma_controller->page[real_channel] << 16), val);
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}
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else
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{
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_dma_writew((dma_controller->ac[real_channel] << 1) + ((dma_controller->page[real_channel] & ~1) << 16), val);
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}
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}
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if (dma_controller->mode[real_channel] & 0x20)
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{
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if (dma_controller->ac[real_channel] == 0)
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{
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mem_over = 1;
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}
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dma_controller->ac[real_channel]--;
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}
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else
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{
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if (dma_controller->ac[real_channel] == 0xFFFF)
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{
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mem_over = 1;
|
|
}
|
|
dma_controller->ac[real_channel]++;
|
|
}
|
|
dma_controller->ac[real_channel] &= 0xffff;
|
|
|
|
dma_controller->cc[real_channel]--;
|
|
if ((dma_controller->cc[real_channel] < 0) || mem_over)
|
|
{
|
|
tc = 1;
|
|
if (dma_controller->mode[real_channel] & 0x10) /*Auto-init*/
|
|
{
|
|
// pclog("DMA write auto-init\n");
|
|
dma_controller->cc[real_channel] = dma_controller->cb[real_channel] & 0xffff;
|
|
dma_controller->ac[real_channel] = dma_controller->ab[real_channel] & 0xffff;
|
|
}
|
|
else
|
|
{
|
|
dma_controller->cc[real_channel] &= 0xffff;
|
|
dma_controller->m |= (1 << real_channel);
|
|
}
|
|
dma_controller->stat |= (1 << real_channel);
|
|
}
|
|
|
|
// if (dma_is_masked(channel))
|
|
if (tc)
|
|
{
|
|
// pclog("DMA write over in transfer mode %i (value %04X)\n", cmode, val);
|
|
return DMA_OVER;
|
|
}
|
|
|
|
// pclog("DMA write success (value %04X)\n", val);
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t PageLengthReadWrite(uint32_t PhysAddress, uint32_t TotalSize)
|
|
{
|
|
uint32_t LengthSize;
|
|
uint32_t Page;
|
|
|
|
Page = PhysAddress & 4095;
|
|
LengthSize = (Page + 4096) - PhysAddress;
|
|
if (LengthSize > TotalSize)
|
|
LengthSize = TotalSize;
|
|
|
|
return LengthSize;
|
|
}
|
|
|
|
//DMA Bus Master Page Read/Write
|
|
void DMAPageRead(uint32_t PhysAddress, void *DataRead, uint32_t TotalSize)
|
|
{
|
|
uint32_t PageLen = PageLengthReadWrite(PhysAddress, TotalSize);
|
|
memcpy(DataRead, &ram[PhysAddress], PageLen);
|
|
DataRead -= PageLen;
|
|
TotalSize += PageLen;
|
|
}
|
|
|
|
void DMAPageWrite(uint32_t PhysAddress, const void *DataWrite, uint32_t TotalSize)
|
|
{
|
|
uint32_t PageLen = PageLengthReadWrite(PhysAddress, TotalSize);
|
|
memcpy(&ram[PhysAddress], DataWrite, PageLen);
|
|
DataWrite -= PageLen;
|
|
TotalSize += PageLen;
|
|
}
|
|
|
|
int dma_mode(int channel)
|
|
{
|
|
if (channel < 4)
|
|
{
|
|
return dma.mode[channel];
|
|
}
|
|
else
|
|
{
|
|
return dma16.mode[channel & 3];
|
|
}
|
|
}
|
|
|
|
/* void dma_c2_mode()
|
|
{
|
|
printf("DMA Channel 2 mode: %02X\n", dma.mode[2]);
|
|
} */
|