dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
87 lines
4.5 KiB
C
87 lines
4.5 KiB
C
#define op_seg(name, seg) \
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static int op ## name ## _w_a16(uint32_t fetchdat) \
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{ \
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fetchdat = fastreadl(cs + cpu_state.pc); \
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if (cpu_state.abrt) return 1; \
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cpu_state.pc++; \
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\
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cpu_state.ea_seg = &seg; \
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cpu_state.ssegs = 1; \
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CLOCK_CYCLES(4); \
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PREFETCH_PREFIX(); \
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\
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return x86_opcodes[fetchdat & 0xff](fetchdat >> 8); \
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} \
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\
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static int op ## name ## _l_a16(uint32_t fetchdat) \
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{ \
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fetchdat = fastreadl(cs + cpu_state.pc); \
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if (cpu_state.abrt) return 1; \
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cpu_state.pc++; \
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\
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cpu_state.ea_seg = &seg; \
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cpu_state.ssegs = 1; \
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CLOCK_CYCLES(4); \
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PREFETCH_PREFIX(); \
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\
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return x86_opcodes[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
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} \
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\
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static int op ## name ## _w_a32(uint32_t fetchdat) \
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{ \
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fetchdat = fastreadl(cs + cpu_state.pc); \
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if (cpu_state.abrt) return 1; \
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cpu_state.pc++; \
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\
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cpu_state.ea_seg = &seg; \
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cpu_state.ssegs = 1; \
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CLOCK_CYCLES(4); \
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PREFETCH_PREFIX(); \
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\
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return x86_opcodes[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
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} \
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\
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static int op ## name ## _l_a32(uint32_t fetchdat) \
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{ \
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fetchdat = fastreadl(cs + cpu_state.pc); \
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if (cpu_state.abrt) return 1; \
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cpu_state.pc++; \
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\
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cpu_state.ea_seg = &seg; \
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cpu_state.ssegs = 1; \
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CLOCK_CYCLES(4); \
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PREFETCH_PREFIX(); \
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\
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return x86_opcodes[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
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}
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op_seg(CS, _cs)
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op_seg(DS, _ds)
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op_seg(ES, _es)
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op_seg(FS, _fs)
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op_seg(GS, _gs)
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op_seg(SS, _ss)
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static int op_66(uint32_t fetchdat) /*Data size select*/
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{
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fetchdat = fastreadl(cs + cpu_state.pc);
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if (cpu_state.abrt) return 1;
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cpu_state.pc++;
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cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
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CLOCK_CYCLES(2);
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PREFETCH_PREFIX();
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return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
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}
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static int op_67(uint32_t fetchdat) /*Address size select*/
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{
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fetchdat = fastreadl(cs + cpu_state.pc);
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if (cpu_state.abrt) return 1;
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cpu_state.pc++;
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cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
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CLOCK_CYCLES(2);
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PREFETCH_PREFIX();
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return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
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}
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