0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
323 lines
6.5 KiB
C
323 lines
6.5 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C611/611A VLB IDE controller.
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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typedef struct
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{
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uint8_t tries,
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in_cfg, cfg_locked,
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regs[19];
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} opti611_t;
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static void opti611_ide_handler(opti611_t *dev);
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static void
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opti611_cfg_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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addr &= 0x0007;
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switch (addr) {
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case 0x0000:
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case 0x0001:
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dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr] = val;
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break;
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case 0x0002:
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dev->regs[0x12] = (val & 0xc1) | 0x02;
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if (val & 0xc0) {
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dev->in_cfg = 0;
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opti611_ide_handler(dev);
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}
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if (val & 0x40)
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dev->cfg_locked = 1;
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break;
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case 0x0003:
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dev->regs[0x03] = (val & 0xdf);
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break;
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case 0x0005:
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dev->regs[0x05] = (dev->regs[0x05] & 0x78) | (val & 0x87);
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break;
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case 0x0006:
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dev->regs[0x06] = val;
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break;
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}
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}
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static void
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opti611_cfg_writew(uint16_t addr, uint16_t val, void *priv)
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{
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opti611_cfg_write(addr, val & 0xff, priv);
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opti611_cfg_write(addr + 1, val >> 8, priv);
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}
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static void
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opti611_cfg_writel(uint16_t addr, uint32_t val, void *priv)
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{
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opti611_cfg_writew(addr, val & 0xffff, priv);
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opti611_cfg_writew(addr + 2, val >> 16, priv);
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}
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static uint8_t
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opti611_cfg_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti611_t *dev = (opti611_t *) priv;
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addr &= 0x0007;
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switch (addr) {
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case 0x0000:
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case 0x0001:
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ret = dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr];
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break;
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case 0x0002:
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ret = ((!!in_smm) << 7);
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if (ret & 0x80)
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ret |= (dev->regs[addr] & 0x7f);
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break;
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case 0x0003: case 0x0004: case 0x0005: case 0x0006:
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ret = dev->regs[addr];
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break;
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}
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return ret;
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}
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static uint16_t
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opti611_cfg_readw(uint16_t addr, void *priv)
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{
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uint16_t ret = 0xffff;
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ret = opti611_cfg_read(addr, priv);
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ret |= (opti611_cfg_read(addr + 1, priv) << 8);
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return ret;
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}
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static uint32_t
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opti611_cfg_readl(uint16_t addr, void *priv)
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{
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uint32_t ret = 0xffffffff;
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ret = opti611_cfg_readw(addr, priv);
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ret |= (opti611_cfg_readw(addr + 2, priv) << 16);
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return ret;
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}
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static void
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opti611_ide_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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uint8_t smibe = (addr & 0x0003);
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | smibe;
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dev->regs[0x04] = val;
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}
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}
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static void
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opti611_ide_writew(uint16_t addr, uint16_t val, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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uint8_t smibe = (addr & 0x0002) | 0x0001;
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | smibe;
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dev->regs[0x04] = 0x00;
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}
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}
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static void
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opti611_ide_writel(uint16_t addr, uint32_t val, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | 0x0003;
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dev->regs[0x04] = 0x00;
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}
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}
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static uint8_t
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opti611_ide_read(uint16_t addr, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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uint8_t smibe = (addr & 0x0003);
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | smibe;
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dev->regs[0x04] = 0x00;
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}
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return 0xff;
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}
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static uint16_t
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opti611_ide_readw(uint16_t addr, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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uint8_t smibe = (addr & 0x0002) | 0x0001;
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if ((addr & 0x0007) == 0x0001) {
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dev->tries = (dev->tries + 1) & 0x01;
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if ((dev->tries == 0x00) && !dev->cfg_locked) {
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dev->in_cfg = 1;
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opti611_ide_handler(dev);
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}
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}
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | smibe;
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dev->regs[0x04] = 0x00;
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}
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return 0xffff;
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}
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static uint32_t
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opti611_ide_readl(uint16_t addr, void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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uint8_t smia9 = (!!(addr & 0x0200)) << 5;
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uint8_t smia2 = (!!(addr & 0x0004)) << 4;
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if (dev->regs[0x03] & 0x02) {
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smi_line = 1;
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dev->regs[0x02] = smia9 | smia2 | 0x0003;
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dev->regs[0x04] = 0x00;
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}
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return 0xffffffff;
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}
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static void
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opti611_ide_handler(opti611_t *dev)
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{
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ide_pri_disable();
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io_removehandler(0x01f0, 0x0007,
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opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
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opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
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dev);
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io_removehandler(0x01f0, 0x0007,
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opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
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opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
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dev);
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if (dev->in_cfg && !dev->cfg_locked) {
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io_sethandler(0x01f0, 0x0007,
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opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
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opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
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dev);
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} else {
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if (dev->regs[0x03] & 0x01)
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ide_pri_enable();
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io_sethandler(0x01f0, 0x0007,
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opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
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opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
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dev);
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}
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}
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static void
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opti611_close(void *priv)
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{
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opti611_t *dev = (opti611_t *) priv;
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free(dev);
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}
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static void *
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opti611_init(const device_t *info)
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{
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opti611_t *dev = (opti611_t *) malloc(sizeof(opti611_t));
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memset(dev, 0, sizeof(opti611_t));
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dev->regs[0x12] = 0x80;
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dev->regs[0x03] = 0x01;
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dev->regs[0x05] = 0x20;
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device_add(&ide_vlb_device);
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opti611_ide_handler(dev);
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return dev;
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}
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const device_t ide_opti611_vlb_device = {
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"OPTi 82C611/82C611A VLB",
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0,
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0,
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opti611_init, opti611_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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