711 lines
26 KiB
C
711 lines
26 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the Texas Instruments TVP3026 true colour RAMDAC
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* family.
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*
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*
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* TODO: Clock and other parts.
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*
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* Authors: TheCollector1995,
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*
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* Copyright 2021 TheCollector1995.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/timer.h>
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#include <86box/video.h>
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#include <86box/vid_svga.h>
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#include <86box/plat_fallthrough.h>
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typedef struct tvp3026_ramdac_t {
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PALETTE extpal;
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uint32_t extpallook[256];
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uint8_t cursor64_data[1024];
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int hwc_y;
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int hwc_x;
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uint8_t ind_idx;
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uint8_t dcc;
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uint8_t dc_init;
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uint8_t ccr;
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uint8_t true_color;
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uint8_t latch_cntl;
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uint8_t mcr;
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uint8_t ppr;
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uint8_t general_cntl;
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uint8_t mclk;
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uint8_t misc;
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uint8_t type;
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uint8_t mode;
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uint8_t pll_addr;
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uint8_t clock_sel;
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struct {
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uint8_t m;
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uint8_t n;
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uint8_t p;
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} pix, mem, loop;
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uint8_t gpio_cntl;
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uint8_t gpio_data;
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uint8_t (*gpio_read)(uint8_t cntl, void *priv);
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void (*gpio_write)(uint8_t cntl, uint8_t val, void *priv);
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void *gpio_priv;
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} tvp3026_ramdac_t;
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static void
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tvp3026_set_bpp(tvp3026_ramdac_t *ramdac, svga_t *svga)
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{
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if ((ramdac->true_color & 0x80) == 0x80) {
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if (ramdac->mcr & 0x08)
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svga->bpp = 8;
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else
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svga->bpp = 4;
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} else {
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switch (ramdac->true_color & 0x0f) {
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case 0x01:
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case 0x03:
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case 0x05:
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svga->bpp = 16;
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break;
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case 0x04:
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svga->bpp = 15;
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break;
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case 0x06:
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case 0x07:
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if (ramdac->true_color & 0x10)
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svga->bpp = 24;
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else
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svga->bpp = 32;
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break;
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case 0x0e:
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case 0x0f:
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svga->bpp = 24;
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break;
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default:
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break;
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}
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}
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svga_recalctimings(svga);
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}
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void
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tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga)
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{
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tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
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uint32_t o32;
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uint8_t *cd;
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uint16_t index;
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uint8_t rs = (addr & 0x03);
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uint16_t da_mask = 0x03ff;
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rs |= (!!rs2 << 2);
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rs |= (!!rs3 << 3);
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switch (rs) {
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case 0x00: /* Palette Write Index Register (RS value = 0000) */
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ramdac->ind_idx = val;
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fallthrough;
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case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
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case 0x03:
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case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
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svga->dac_pos = 0;
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svga->dac_status = addr & 0x03;
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svga->dac_addr = val;
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if (svga->dac_status)
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svga->dac_addr = (svga->dac_addr + 1) & da_mask;
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break;
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case 0x01: /* Palette Data Register (RS value = 0001) */
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case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
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svga_out(addr, val, svga);
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break;
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case 0x05: /* Ext Palette Data Register (RS value = 0101) */
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svga->dac_status = 0;
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svga->fullchange = changeframecount;
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switch (svga->dac_pos) {
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case 0:
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svga->dac_r = val;
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svga->dac_pos++;
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break;
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case 1:
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svga->dac_g = val;
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svga->dac_pos++;
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break;
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case 2:
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index = svga->dac_addr & 3;
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ramdac->extpal[index].r = svga->dac_r;
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ramdac->extpal[index].g = svga->dac_g;
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ramdac->extpal[index].b = val;
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if (svga->ramdac_type == RAMDAC_8BIT)
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ramdac->extpallook[index] = makecol32(ramdac->extpal[index].r, ramdac->extpal[index].g, ramdac->extpal[index].b);
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else
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ramdac->extpallook[index] = makecol32(video_6to8[ramdac->extpal[index].r & 0x3f], video_6to8[ramdac->extpal[index].g & 0x3f], video_6to8[ramdac->extpal[index].b & 0x3f]);
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if (svga->ext_overscan && !index) {
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o32 = svga->overscan_color;
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svga->overscan_color = ramdac->extpallook[0];
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if (o32 != svga->overscan_color)
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svga_recalctimings(svga);
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}
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svga->dac_addr = (svga->dac_addr + 1) & 0xff;
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svga->dac_pos = 0;
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break;
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default:
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break;
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}
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break;
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case 0x09: /* Direct Cursor Control (RS value = 1001) */
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ramdac->dcc = val;
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if (ramdac->ccr & 0x80) {
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svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
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svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
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svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
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svga->dac_hwcursor.ena = !!(val & 0x03);
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ramdac->mode = val & 0x03;
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}
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break;
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case 0x0a: /* Indexed Data (RS value = 1010) */
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switch (ramdac->ind_idx) {
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case 0x06: /* Indirect Cursor Control */
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ramdac->ccr = val;
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if (!(ramdac->ccr & 0x80)) {
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svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
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svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
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svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
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svga->dac_hwcursor.ena = !!(val & 0x03);
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ramdac->mode = val & 0x03;
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} else {
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svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
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svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
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svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
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svga->dac_hwcursor.ena = !!(ramdac->dcc & 0x03);
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ramdac->mode = ramdac->dcc & 0x03;
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}
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break;
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case 0x0f: /* Latch Control */
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ramdac->latch_cntl = val;
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break;
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case 0x18: /* True Color Control */
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ramdac->true_color = val;
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tvp3026_set_bpp(ramdac, svga);
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break;
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case 0x19: /* Multiplex Control */
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ramdac->mcr = val;
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tvp3026_set_bpp(ramdac, svga);
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break;
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case 0x1a: /* Clock Selection */
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ramdac->clock_sel = val;
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break;
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case 0x1c: /* Palette-Page Register */
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ramdac->ppr = val;
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break;
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case 0x1d: /* General Control Register */
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ramdac->general_cntl = val;
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break;
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case 0x1e: /* Miscellaneous Control */
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ramdac->misc = val;
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svga->ramdac_type = (val & 0x08) ? RAMDAC_8BIT : RAMDAC_6BIT;
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break;
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case 0x2a: /* General-Purpose I/O Control */
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ramdac->gpio_cntl = val;
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if (ramdac->gpio_write)
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ramdac->gpio_write(ramdac->gpio_cntl, ramdac->gpio_data, ramdac->gpio_priv);
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break;
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case 0x2b: /* General-Purpose I/O Data */
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ramdac->gpio_data = val;
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if (ramdac->gpio_write)
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ramdac->gpio_write(ramdac->gpio_cntl, ramdac->gpio_data, ramdac->gpio_priv);
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break;
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case 0x2c: /* PLL Address */
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ramdac->pll_addr = val;
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break;
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case 0x2d: /* Pixel clock PLL data */
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switch (ramdac->pll_addr & 3) {
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case 0:
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ramdac->pix.n = val;
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break;
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case 1:
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ramdac->pix.m = val;
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break;
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case 2:
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ramdac->pix.p = val;
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break;
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default:
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break;
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}
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ramdac->pll_addr = ((ramdac->pll_addr + 1) & 3) | (ramdac->pll_addr & 0xfc);
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break;
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case 0x2e: /* Memory Clock PLL Data */
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switch ((ramdac->pll_addr >> 2) & 3) {
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case 0:
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ramdac->mem.n = val;
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break;
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case 1:
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ramdac->mem.m = val;
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break;
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case 2:
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ramdac->mem.p = val;
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break;
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default:
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break;
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}
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ramdac->pll_addr = ((ramdac->pll_addr + 4) & 0x0c) | (ramdac->pll_addr & 0xf3);
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break;
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case 0x2f: /* Loop Clock PLL Data */
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switch ((ramdac->pll_addr >> 4) & 3) {
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case 0:
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ramdac->loop.n = val;
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break;
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case 1:
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ramdac->loop.m = val;
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break;
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case 2:
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ramdac->loop.p = val;
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break;
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default:
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break;
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}
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ramdac->pll_addr = ((ramdac->pll_addr + 0x10) & 0x30) | (ramdac->pll_addr & 0xcf);
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break;
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case 0x39: /* MCLK/Loop Clock Control */
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ramdac->mclk = val;
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break;
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default:
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break;
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}
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break;
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case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
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index = (svga->dac_addr & da_mask) | ((ramdac->ccr & 0x0c) << 6);
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cd = (uint8_t *) ramdac->cursor64_data;
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cd[index] = val;
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svga->dac_addr = (svga->dac_addr + 1) & da_mask;
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break;
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case 0x0c: /* Cursor X Low Register (RS value = 1100) */
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ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
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svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
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break;
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case 0x0d: /* Cursor X High Register (RS value = 1101) */
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ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | ((val & 0x0f) << 8);
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svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
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break;
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case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
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ramdac->hwc_y = (ramdac->hwc_y & 0x0f00) | val;
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svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
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break;
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case 0x0f: /* Cursor Y High Register (RS value = 1111) */
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ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | ((val & 0x0f) << 8);
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svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
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break;
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default:
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break;
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}
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return;
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}
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uint8_t
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tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga)
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{
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tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
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uint8_t temp = 0xff;
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const uint8_t *cd;
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uint16_t index;
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uint8_t rs = (addr & 0x03);
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uint16_t da_mask = 0x03ff;
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rs |= (!!rs2 << 2);
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rs |= (!!rs3 << 3);
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switch (rs) {
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case 0x00: /* Palette Write Index Register (RS value = 0000) */
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case 0x01: /* Palette Data Register (RS value = 0001) */
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case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
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case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
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temp = svga_in(addr, svga);
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break;
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case 0x03: /* Palette Read Index Register (RS value = 0011) */
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case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
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temp = svga->dac_addr & 0xff;
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break;
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case 0x05: /* Ext Palette Data Register (RS value = 0101) */
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index = (svga->dac_addr - 1) & 3;
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svga->dac_status = 3;
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switch (svga->dac_pos) {
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case 0:
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svga->dac_pos++;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].r;
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else
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temp = ramdac->extpal[index].r & 0x3f;
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break;
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case 1:
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svga->dac_pos++;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].g;
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else
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temp = ramdac->extpal[index].g & 0x3f;
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break;
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case 2:
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svga->dac_pos = 0;
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svga->dac_addr = svga->dac_addr + 1;
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if (svga->ramdac_type == RAMDAC_8BIT)
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temp = ramdac->extpal[index].b;
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else
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temp = ramdac->extpal[index].b & 0x3f;
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break;
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default:
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break;
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}
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break;
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case 0x09: /* Direct Cursor Control (RS value = 1001) */
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temp = ramdac->dcc;
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break;
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case 0x0a: /* Indexed Data (RS value = 1010) */
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switch (ramdac->ind_idx) {
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case 0x01: /* Silicon Revision */
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temp = 0x00;
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break;
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case 0x06: /* Indirect Cursor Control */
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temp = ramdac->ccr;
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break;
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case 0x0f: /* Latch Control */
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temp = ramdac->latch_cntl;
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break;
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case 0x18: /* True Color Control */
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temp = ramdac->true_color;
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break;
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case 0x19: /* Multiplex Control */
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temp = ramdac->mcr;
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break;
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case 0x1a: /* Clock Selection */
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temp = ramdac->clock_sel;
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break;
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case 0x1c: /* Palette-Page Register */
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temp = ramdac->ppr;
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break;
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case 0x1d: /* General Control Register */
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temp = ramdac->general_cntl;
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break;
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case 0x1e: /* Miscellaneous Control */
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temp = ramdac->misc;
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break;
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case 0x2a: /* General-Purpose I/O Control */
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temp = ramdac->gpio_cntl;
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break;
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case 0x2b: /* General-Purpose I/O Data */
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if (ramdac->gpio_read) {
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temp = 0xe0 | (ramdac->gpio_cntl & 0x1f); /* keep upper bits untouched */
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ramdac->gpio_data = (ramdac->gpio_data & temp) | (ramdac->gpio_read(ramdac->gpio_cntl, ramdac->gpio_priv) & ~temp);
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}
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temp = ramdac->gpio_data;
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break;
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case 0x2c: /* PLL Address */
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temp = ramdac->pll_addr;
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break;
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case 0x2d: /* Pixel clock PLL data */
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switch (ramdac->pll_addr & 3) {
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case 0:
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temp = ramdac->pix.n;
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break;
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case 1:
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temp = ramdac->pix.m;
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break;
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case 2:
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temp = ramdac->pix.p;
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break;
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case 3:
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temp = 0x40; /*PLL locked to frequency*/
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break;
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default:
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break;
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}
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break;
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case 0x2e: /* Memory Clock PLL Data */
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switch ((ramdac->pll_addr >> 2) & 3) {
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case 0:
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temp = ramdac->mem.n;
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break;
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case 1:
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temp = ramdac->mem.m;
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break;
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case 2:
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temp = ramdac->mem.p;
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break;
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case 3:
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temp = 0x40; /*PLL locked to frequency*/
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break;
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default:
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break;
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}
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break;
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case 0x2f: /* Loop Clock PLL Data */
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switch ((ramdac->pll_addr >> 4) & 3) {
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case 0:
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temp = ramdac->loop.n;
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break;
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case 1:
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temp = ramdac->loop.m;
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break;
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case 2:
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temp = ramdac->loop.p;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 0x39: /* MCLK/Loop Clock Control */
|
|
temp = ramdac->mclk;
|
|
break;
|
|
case 0x3f: /* ID */
|
|
temp = 0x26;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
|
|
index = ((svga->dac_addr - 1) & da_mask) | ((ramdac->ccr & 0x0c) << 6);
|
|
cd = (uint8_t *) ramdac->cursor64_data;
|
|
temp = cd[index];
|
|
|
|
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
|
|
break;
|
|
case 0x0c: /* Cursor X Low Register (RS value = 1100) */
|
|
temp = ramdac->hwc_x & 0xff;
|
|
break;
|
|
case 0x0d: /* Cursor X High Register (RS value = 1101) */
|
|
temp = (ramdac->hwc_x >> 8) & 0xff;
|
|
break;
|
|
case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
|
|
temp = ramdac->hwc_y & 0xff;
|
|
break;
|
|
case 0x0f: /* Cursor Y High Register (RS value = 1111) */
|
|
temp = (ramdac->hwc_y >> 8) & 0xff;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return temp;
|
|
}
|
|
|
|
void
|
|
tvp3026_recalctimings(void *priv, svga_t *svga)
|
|
{
|
|
const tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
|
|
|
|
svga->interlace = (ramdac->ccr & 0x40);
|
|
/* TODO: Figure out gamma correction for 15/16 bpp color. */
|
|
svga->lut_map = !!(svga->bpp >= 24 && (ramdac->true_color & 0xf0) != 0x00);
|
|
}
|
|
|
|
void
|
|
tvp3026_hwcursor_draw(svga_t *svga, int displine)
|
|
{
|
|
int comb;
|
|
int b0;
|
|
int b1;
|
|
uint16_t dat[2];
|
|
int offset = svga->dac_hwcursor_latch.x + svga->dac_hwcursor_latch.xoff;
|
|
int pitch;
|
|
int bppl;
|
|
int mode;
|
|
int x_pos;
|
|
int y_pos;
|
|
uint32_t clr1;
|
|
uint32_t clr2;
|
|
uint32_t clr3;
|
|
uint32_t *p;
|
|
const uint8_t *cd;
|
|
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) svga->ramdac;
|
|
|
|
clr1 = ramdac->extpallook[1];
|
|
clr2 = ramdac->extpallook[2];
|
|
clr3 = ramdac->extpallook[3];
|
|
|
|
/* The planes come in two parts, and each plane is 1bpp,
|
|
so a 32x32 cursor has 4 bytes per line, and a 64x64
|
|
cursor has 8 bytes per line. */
|
|
pitch = (svga->dac_hwcursor_latch.cur_xsize >> 3); /* Bytes per line. */
|
|
/* A 32x32 cursor has 128 bytes per line, and a 64x64
|
|
cursor has 512 bytes per line. */
|
|
bppl = (pitch * svga->dac_hwcursor_latch.cur_ysize); /* Bytes per plane. */
|
|
mode = ramdac->mode;
|
|
|
|
if (svga->interlace && svga->dac_hwcursor_oddeven)
|
|
svga->dac_hwcursor_latch.addr += pitch;
|
|
|
|
cd = (uint8_t *) ramdac->cursor64_data;
|
|
|
|
for (int x = 0; x < svga->dac_hwcursor_latch.cur_xsize; x += 16) {
|
|
dat[0] = (cd[svga->dac_hwcursor_latch.addr] << 8) | cd[svga->dac_hwcursor_latch.addr + 1];
|
|
dat[1] = (cd[svga->dac_hwcursor_latch.addr + bppl] << 8) | cd[svga->dac_hwcursor_latch.addr + bppl + 1];
|
|
|
|
for (uint8_t xx = 0; xx < 16; xx++) {
|
|
b0 = (dat[0] >> (15 - xx)) & 1;
|
|
b1 = (dat[1] >> (15 - xx)) & 1;
|
|
comb = (b0 | (b1 << 1));
|
|
|
|
y_pos = displine;
|
|
x_pos = offset + svga->x_add;
|
|
p = svga->monitor->target_buffer->line[y_pos];
|
|
|
|
if (offset >= svga->dac_hwcursor_latch.x) {
|
|
switch (mode) {
|
|
case 1: /* Three Color */
|
|
switch (comb) {
|
|
case 1:
|
|
p[x_pos] = clr1;
|
|
break;
|
|
case 2:
|
|
p[x_pos] = clr2;
|
|
break;
|
|
case 3:
|
|
p[x_pos] = clr3;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 2: /* XGA */
|
|
switch (comb) {
|
|
case 0:
|
|
p[x_pos] = clr1;
|
|
break;
|
|
case 1:
|
|
p[x_pos] = clr2;
|
|
break;
|
|
case 3:
|
|
p[x_pos] ^= 0xffffff;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 3: /* X-Windows */
|
|
switch (comb) {
|
|
case 2:
|
|
p[x_pos] = clr1;
|
|
break;
|
|
case 3:
|
|
p[x_pos] = clr2;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
offset++;
|
|
}
|
|
svga->dac_hwcursor_latch.addr += 2;
|
|
}
|
|
|
|
if (svga->interlace && !svga->dac_hwcursor_oddeven)
|
|
svga->dac_hwcursor_latch.addr += pitch;
|
|
}
|
|
|
|
float
|
|
tvp3026_getclock(int clock, void *priv)
|
|
{
|
|
const tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
|
|
int n;
|
|
int m;
|
|
int pl;
|
|
float f_vco;
|
|
float f_pll;
|
|
|
|
if (clock == 0)
|
|
return 25175000.0;
|
|
if (clock == 1)
|
|
return 28322000.0;
|
|
|
|
/*Fvco = 8 x Fref x (65 - M) / (65 - N)*/
|
|
/*Fpll = Fvco / 2^P*/
|
|
n = ramdac->pix.n & 0x3f;
|
|
m = ramdac->pix.m & 0x3f;
|
|
pl = ramdac->pix.p & 0x03;
|
|
f_vco = 8.0f * 14318184 * (float) (65 - m) / (float) (65 - n);
|
|
f_pll = f_vco / (float) (1 << pl);
|
|
|
|
return f_pll;
|
|
}
|
|
|
|
void
|
|
tvp3026_gpio(uint8_t (*read)(uint8_t cntl, void *priv),
|
|
void (*write)(uint8_t cntl, uint8_t val, void *priv),
|
|
void *cb_priv, void *priv)
|
|
{
|
|
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
|
|
|
|
ramdac->gpio_read = read;
|
|
ramdac->gpio_write = write;
|
|
ramdac->gpio_priv = cb_priv;
|
|
}
|
|
|
|
void *
|
|
tvp3026_ramdac_init(const device_t *info)
|
|
{
|
|
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) malloc(sizeof(tvp3026_ramdac_t));
|
|
memset(ramdac, 0, sizeof(tvp3026_ramdac_t));
|
|
|
|
ramdac->type = info->local;
|
|
|
|
ramdac->latch_cntl = 0x06;
|
|
ramdac->true_color = 0x80;
|
|
ramdac->mcr = 0x98;
|
|
ramdac->clock_sel = 0x07;
|
|
ramdac->mclk = 0x18;
|
|
|
|
return ramdac;
|
|
}
|
|
|
|
static void
|
|
tvp3026_ramdac_close(void *priv)
|
|
{
|
|
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
|
|
|
|
if (ramdac)
|
|
free(ramdac);
|
|
}
|
|
|
|
const device_t tvp3026_ramdac_device = {
|
|
.name = "TI TVP3026 RAMDAC",
|
|
.internal_name = "tvp3026_ramdac",
|
|
.flags = 0,
|
|
.local = 0,
|
|
.init = tvp3026_ramdac_init,
|
|
.close = tvp3026_ramdac_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|