160 lines
3.8 KiB
C
160 lines
3.8 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C291 chipset.
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* Authors: plant/nerd73, Tiseno100
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*
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* Copyright 2020 plant/nerd73.
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* Copyright 2021 Tiseno100.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#ifdef ENABLE_OPTI291_LOG
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int opti291_do_log = ENABLE_OPTI291_LOG;
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static void
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opti291_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti291_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define opti291_log(fmt, ...)
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#endif
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typedef struct
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{
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uint8_t index, regs[256];
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port_92_t *port_92;
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} opti291_t;
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static void opti291_recalc(opti291_t *dev)
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{
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mem_set_mem_state_both(0xf0000, 0x10000, (!(dev->regs[0x23] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
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for (uint32_t i = 0; i < 4; i++)
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{
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x26] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : ((dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
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mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, ((dev->regs[0x25] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : ((dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
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mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, ((dev->regs[0x24] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : ((dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
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}
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flushmmucache();
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}
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static void
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opti291_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti291_t *dev = (opti291_t *)priv;
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switch (addr)
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{
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case 0x22:
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dev->index = val;
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break;
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case 0x24:
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opti291_log("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val);
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switch (dev->index)
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{
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case 0x20:
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dev->regs[dev->index] = val & 0x3f;
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break;
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case 0x21:
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dev->regs[dev->index] = val & 0xf3;
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break;
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case 0x22:
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dev->regs[dev->index] = val;
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break;
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case 0x23:
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case 0x24:
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case 0x25:
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case 0x26:
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dev->regs[dev->index] = val;
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opti291_recalc(dev);
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break;
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case 0x27:
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case 0x28:
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dev->regs[dev->index] = val;
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break;
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case 0x29:
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dev->regs[dev->index] = val & 0x0f;
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break;
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case 0x2a:
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case 0x2b:
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case 0x2c:
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dev->regs[dev->index] = val;
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break;
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}
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break;
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}
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}
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static uint8_t
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opti291_read(uint16_t addr, void *priv)
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{
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opti291_t *dev = (opti291_t *)priv;
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return (addr == 0x24) ? dev->regs[dev->index] : 0xff;
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}
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static void
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opti291_close(void *priv)
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{
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opti291_t *dev = (opti291_t *)priv;
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free(dev);
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}
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static void *
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opti291_init(const device_t *info)
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{
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opti291_t *dev = (opti291_t *)malloc(sizeof(opti291_t));
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memset(dev, 0, sizeof(opti291_t));
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io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
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io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
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dev->regs[0x22] = 0xf0;
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dev->regs[0x23] = 0x40;
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dev->regs[0x28] = 0x08;
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dev->regs[0x29] = 0xa0;
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device_add(&port_92_device);
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opti291_recalc(dev);
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return dev;
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}
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const device_t opti291_device = {
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"OPTi 82C291",
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0,
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0,
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opti291_init,
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opti291_close,
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NULL,
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{NULL},
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NULL,
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NULL,
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NULL};
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