254 lines
6.3 KiB
C
254 lines
6.3 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of a generic PIIX4-compatible SMBus host controller.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/timer.h>
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#include <86box/smbus.h>
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#include <86box/smbus_piix4.h>
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#ifdef ENABLE_SMBUS_PIIX4_LOG
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int smbus_piix4_do_log = ENABLE_SMBUS_PIIX4_LOG;
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static void
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smbus_piix4_log(const char *fmt, ...)
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{
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va_list ap;
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if (smbus_piix4_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define smbus_piix4_log(fmt, ...)
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#endif
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static uint8_t
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smbus_piix4_read(uint16_t addr, void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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uint8_t ret = 0x00;
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switch (addr - dev->io_base) {
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case 0x00:
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ret = dev->stat;
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break;
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case 0x02:
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dev->index = 0; /* reading from this resets the block data index */
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ret = dev->ctl;
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break;
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case 0x03:
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ret = dev->cmd;
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break;
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case 0x04:
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ret = dev->addr;
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break;
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case 0x05:
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ret = dev->data0;
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break;
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case 0x06:
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ret = dev->data1;
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break;
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case 0x07:
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ret = dev->data[dev->index++];
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if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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}
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smbus_piix4_log("SMBus PIIX4: read(%02x) = %02x\n", addr, ret);
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return ret;
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}
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static void
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smbus_piix4_write(uint16_t addr, uint8_t val, void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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uint8_t smbus_addr, smbus_read, prev_stat;
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uint16_t temp;
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smbus_piix4_log("SMBus PIIX4: write(%02x, %02x)\n", addr, val);
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prev_stat = dev->next_stat;
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dev->next_stat = 0;
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switch (addr - dev->io_base) {
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case 0x00:
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/* some status bits are reset by writing 1 to them */
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for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr = smbus_addr << 1) {
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if (val & smbus_addr)
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dev->stat = dev->stat & ~smbus_addr;
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}
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break;
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case 0x02:
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dev->ctl = val & ~(0x40); /* START always reads 0 */
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if (val & 0x02) { /* cancel an in-progress command if KILL is set */
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/* cancel only if a command is in progress */
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if (prev_stat) {
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dev->stat = 0x10; /* raise FAILED */
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timer_disable(&dev->response_timer);
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}
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}
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if (val & 0x40) { /* dispatch command if START is set */
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smbus_addr = (dev->addr >> 1);
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if (!smbus_has_device(smbus_addr)) {
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/* raise DEV_ERR if no device is at this address */
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dev->next_stat = 0x4;
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break;
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}
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smbus_read = (dev->addr & 0x01);
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/* decode the 3-bit command protocol */
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switch ((val >> 2) & 0x7) {
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case 0x0: /* quick R/W */
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dev->next_stat = 0x2;
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break;
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case 0x1: /* byte R/W */
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if (smbus_read)
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dev->data0 = smbus_read_byte(smbus_addr);
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else
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smbus_write_byte(smbus_addr, dev->data0);
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dev->next_stat = 0x2;
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break;
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case 0x2: /* byte data R/W */
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if (smbus_read)
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dev->data0 = smbus_read_byte_cmd(smbus_addr, dev->cmd);
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else
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smbus_write_byte_cmd(smbus_addr, dev->cmd, dev->data0);
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dev->next_stat = 0x2;
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break;
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case 0x3: /* word data R/W */
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if (smbus_read) {
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temp = smbus_read_word_cmd(smbus_addr, dev->cmd);
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dev->data0 = (temp & 0xFF);
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dev->data1 = (temp >> 8);
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} else {
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temp = (dev->data1 << 8) | dev->data0;
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smbus_write_word_cmd(smbus_addr, dev->cmd, temp);
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}
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dev->next_stat = 0x2;
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break;
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case 0x5: /* block R/W */
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if (smbus_read)
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dev->data0 = smbus_read_block_cmd(smbus_addr, dev->cmd, dev->data, SMBUS_PIIX4_BLOCK_DATA_SIZE);
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else
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smbus_write_block_cmd(smbus_addr, dev->cmd, dev->data, dev->data0);
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dev->next_stat = 0x2;
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break;
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default:
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/* other command protocols have undefined behavior, but raise DEV_ERR to be safe */
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dev->next_stat = 0x4;
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break;
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}
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}
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break;
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case 0x03:
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dev->cmd = val;
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break;
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case 0x04:
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dev->addr = val;
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break;
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case 0x05:
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dev->data0 = val;
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break;
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case 0x06:
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dev->data1 = val;
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break;
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case 0x07:
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dev->data[dev->index++] = val;
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if (dev->index >= SMBUS_PIIX4_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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}
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/* if a status register update was given, dispatch it after 10ms to ensure nothing breaks */
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if (dev->next_stat) {
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dev->stat = 0x1; /* raise HOST_BUSY while waiting */
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timer_disable(&dev->response_timer);
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timer_set_delay_u64(&dev->response_timer, 10 * TIMER_USEC);
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}
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}
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static void
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smbus_piix4_response(void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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/* dispatch the status register update */
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dev->stat = dev->next_stat;
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}
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void
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smbus_piix4_remap(smbus_piix4_t *dev, uint16_t new_io_base, uint8_t enable)
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{
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if (dev->io_base != 0x0000)
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io_removehandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev);
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dev->io_base = new_io_base;
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smbus_piix4_log("SMBus PIIX4: remap to %04Xh\n", dev->io_base);
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if (enable && (dev->io_base != 0x0000))
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io_sethandler(dev->io_base, 0x10, smbus_piix4_read, NULL, NULL, smbus_piix4_write, NULL, NULL, dev);
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}
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static void *
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smbus_piix4_init(const device_t *info)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) malloc(sizeof(smbus_piix4_t));
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memset(dev, 0, sizeof(smbus_piix4_t));
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smbus_init();
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timer_add(&dev->response_timer, smbus_piix4_response, dev, 0);
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return dev;
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}
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static void
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smbus_piix4_close(void *priv)
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{
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smbus_piix4_t *dev = (smbus_piix4_t *) priv;
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free(dev);
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}
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const device_t piix4_smbus_device = {
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"PIIX4-compatible SMBus Host Controller",
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DEVICE_AT,
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0,
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smbus_piix4_init, smbus_piix4_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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