a412ceb4d9
Extensively cleaned up and changed the CD-ROM code; Removed CD-ROM IOCTTL (it was causing performance and stability issues); Turned a lot of things into device_t's; Added the PS/1 Model 2011 XTA and standalone XTA hard disk controllers, ported from Varcem; Numerous FDC fixes for the PS/1 Model 2121; NVR changes ported from Varcem; The PCap code no longer requires libpcap to be compiled; Numerous fixes to various SCSI controllers; Updated NukedOPL to 1.8; Fixes to OpenAL initialization and closing, should give less Audio issues now; Revorked parts of the common (S)VGA code (also based on code from QEMU); Removed the Removable SCSI hard disks (they were a never finished experiment so there was no need to keep them there); Cleaned up the SCSI hard disk and Iomega ZIP code (but more cleanups of that are coming in the future); In some occasions (IDE hard disks in multiple sector mode and SCSI hard disks) the status bar icon is no longer updated, should improve performance a bit; Redid the way the tertiary and quaternary IDE controllers are configured (and they are now device_t's); Extensively reworked the IDE code and fixed quite a few bugs; Fixes to XT MFM, AT MFM, and AT ESDI code; Some changes to XTIDE and MCA ESDI code; Some fixes to the CD-ROM image handler.
332 lines
6.5 KiB
C
332 lines
6.5 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SMC FDC37C663 and FDC37C665 Super
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* I/O Chips.
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*
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* Version: @(#)sio_fdc37c66x.c 1.0.11 2018/04/04
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2018 Sarah Walker.
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* Copyright 2016-2018 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "io.h"
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#include "device.h"
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#include "pci.h"
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#include "lpt.h"
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#include "serial.h"
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#include "disk/hdc.h"
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#include "disk/hdc_ide.h"
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#include "floppy/fdd.h"
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#include "floppy/fdc.h"
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#include "sio.h"
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static uint8_t fdc37c66x_lock[2];
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static int fdc37c66x_curreg;
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static uint8_t fdc37c66x_regs[16];
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static int com3_addr, com4_addr;
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static fdc_t *fdc37c66x_fdc;
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static void write_lock(uint8_t val)
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{
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if (val == 0x55 && fdc37c66x_lock[1] == 0x55)
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fdc_3f1_enable(fdc37c66x_fdc, 0);
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if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55 && val != 0x55)
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fdc_3f1_enable(fdc37c66x_fdc, 1);
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fdc37c66x_lock[0] = fdc37c66x_lock[1];
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fdc37c66x_lock[1] = val;
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}
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static void ide_handler()
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{
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#if 0
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uint16_t or_value = 0;
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if ((romset == ROM_440FX) || (romset == ROM_R418) || (romset == ROM_MB500N))
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{
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return;
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}
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ide_pri_disable();
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if (fdc37c66x_regs[0] & 1)
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{
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if (fdc37c66x_regs[5] & 2)
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{
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or_value = 0;
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}
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else
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{
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or_value = 0x800;
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}
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ide_set_base(0, 0x170 | or_value);
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ide_set_side(0, 0x376 | or_value);
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ide_pri_enable();
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}
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#endif
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}
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static void set_com34_addr()
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{
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switch (fdc37c66x_regs[1] & 0x60)
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{
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case 0x00:
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com3_addr = 0x338;
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com4_addr = 0x238;
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break;
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case 0x20:
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com3_addr = 0x3e8;
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com4_addr = 0x2e8;
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break;
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case 0x40:
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com3_addr = 0x3e8;
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com4_addr = 0x2e0;
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break;
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case 0x60:
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com3_addr = 0x220;
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com4_addr = 0x228;
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break;
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}
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}
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static void set_serial1_addr()
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{
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if (fdc37c66x_regs[2] & 4)
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{
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switch (fdc37c66x_regs[2] & 3)
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{
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case 0:
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serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
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break;
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case 1:
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serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
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break;
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case 2:
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serial_setup(1, com3_addr, 4);
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break;
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case 3:
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serial_setup(1, com4_addr, 3);
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break;
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}
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}
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}
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static void set_serial2_addr()
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{
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if (fdc37c66x_regs[2] & 0x40)
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{
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switch (fdc37c66x_regs[2] & 0x30)
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{
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case 0:
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serial_setup(2, SERIAL1_ADDR, SERIAL1_IRQ);
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break;
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case 1:
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serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
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break;
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case 2:
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serial_setup(2, com3_addr, 4);
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break;
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case 3:
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serial_setup(2, com4_addr, 3);
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break;
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}
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}
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}
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static void lpt1_handler()
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{
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lpt1_remove();
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switch (fdc37c66x_regs[1] & 3)
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{
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case 1:
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lpt1_init(0x3bc);
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break;
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case 2:
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lpt1_init(0x378);
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break;
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case 3:
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lpt1_init(0x278);
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break;
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}
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}
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static void fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
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{
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uint8_t valxor = 0;
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if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55)
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{
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if (port == 0x3f0)
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{
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if (val == 0xaa)
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write_lock(val);
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else
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fdc37c66x_curreg = val;
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#if 0
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if (fdc37c66x_curreg != 0)
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{
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fdc37c66x_curreg = val & 0xf;
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}
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else
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{
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/* Hardcode the IDE to AT type. */
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fdc37c66x_curreg = (val & 0xf) | 2;
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}
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#endif
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}
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else
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{
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if (fdc37c66x_curreg > 15)
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return;
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valxor = val ^ fdc37c66x_regs[fdc37c66x_curreg];
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fdc37c66x_regs[fdc37c66x_curreg] = val;
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switch(fdc37c66x_curreg)
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{
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case 0:
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if (valxor & 1)
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{
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ide_handler();
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}
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break;
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case 1:
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if (valxor & 3)
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{
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lpt1_handler();
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}
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if (valxor & 0x60)
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{
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serial_remove(1);
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set_com34_addr();
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set_serial1_addr();
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set_serial2_addr();
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}
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break;
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case 2:
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if (valxor & 7)
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{
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serial_remove(1);
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set_serial1_addr();
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}
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if (valxor & 0x70)
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{
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serial_remove(2);
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set_serial2_addr();
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}
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break;
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case 3:
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if (valxor & 2)
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{
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fdc_update_enh_mode(fdc37c66x_fdc, (fdc37c66x_regs[3] & 2) ? 1 : 0);
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}
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break;
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case 5:
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if (valxor & 2)
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{
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ide_handler();
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}
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if (valxor & 0x18)
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{
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fdc_update_densel_force(fdc37c66x_fdc, (fdc37c66x_regs[5] & 0x18) >> 3);
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}
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if (valxor & 0x20)
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{
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fdc_set_swap(fdc37c66x_fdc, (fdc37c66x_regs[5] & 0x20) >> 5);
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}
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break;
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}
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}
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}
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else
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{
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if (port == 0x3f0)
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write_lock(val);
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}
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}
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static uint8_t fdc37c66x_read(uint16_t port, void *priv)
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{
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if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55)
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{
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if (port == 0x3f1)
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return fdc37c66x_regs[fdc37c66x_curreg];
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}
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return 0xff;
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}
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static void fdc37c66x_reset(void)
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{
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com3_addr = 0x338;
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com4_addr = 0x238;
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serial_remove(1);
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serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
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serial_remove(2);
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serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
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lpt2_remove();
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lpt1_remove();
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lpt1_init(0x378);
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fdc_reset(fdc37c66x_fdc);
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memset(fdc37c66x_lock, 0, 2);
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memset(fdc37c66x_regs, 0, 16);
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fdc37c66x_regs[0x0] = 0x3a;
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fdc37c66x_regs[0x1] = 0x9f;
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fdc37c66x_regs[0x2] = 0xdc;
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fdc37c66x_regs[0x3] = 0x78;
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fdc37c66x_regs[0x6] = 0xff;
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fdc37c66x_regs[0xe] = 0x01;
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}
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static void fdc37c663_reset(void)
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{
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fdc37c66x_reset();
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fdc37c66x_regs[0xd] = 0x63;
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}
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static void fdc37c665_reset(void)
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{
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fdc37c66x_reset();
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fdc37c66x_regs[0xd] = 0x65;
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}
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void fdc37c663_init()
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{
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fdc37c66x_fdc = device_add(&fdc_at_smc_device);
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io_sethandler(0x03f0, 0x0002, fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, NULL);
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fdc37c663_reset();
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}
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void fdc37c665_init()
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{
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fdc37c66x_fdc = device_add(&fdc_at_smc_device);
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io_sethandler(0x03f0, 0x0002, fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, NULL);
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fdc37c665_reset();
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}
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