715 lines
19 KiB
C
715 lines
19 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* CPU type handler.
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* leilei,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2018 Sarah Walker.
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* Copyright 2016-2018 leilei.
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* Copyright 2016,2018 Miran Grca.
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*/
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#ifndef EMU_CPU_H
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# define EMU_CPU_H
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enum {
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FPU_NONE,
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FPU_8087,
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FPU_287,
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FPU_287XL,
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FPU_387,
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FPU_487SX,
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FPU_INTERNAL
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};
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enum {
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CPU_8088 = 1, /* 808x class CPUs */
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CPU_8086,
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#ifdef USE_NEC_808X
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CPU_V20, /* NEC 808x class CPUs - future proofing */
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CPU_V30,
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#endif
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CPU_286, /* 286 class CPUs */
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CPU_386SX, /* 386 class CPUs */
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CPU_IBM386SLC,
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CPU_IBM486SLC,
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CPU_386DX,
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CPU_IBM486BL,
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CPU_RAPIDCAD,
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CPU_486SLC,
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CPU_486DLC,
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CPU_i486SX, /* 486 class CPUs */
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CPU_Am486SX,
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CPU_Cx486S,
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CPU_i486DX,
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CPU_Am486DX,
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CPU_Am486DXL,
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CPU_Cx486DX,
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CPU_STPC,
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CPU_i486SX_SLENH,
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CPU_i486DX_SLENH,
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CPU_ENH_Am486DX,
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CPU_Cx5x86,
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CPU_P24T,
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CPU_WINCHIP, /* 586 class CPUs */
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CPU_WINCHIP2,
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CPU_PENTIUM,
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CPU_PENTIUMMMX,
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CPU_Cx6x86,
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CPU_Cx6x86MX,
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CPU_Cx6x86L,
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CPU_CxGX1,
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CPU_K5,
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CPU_5K86,
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CPU_K6,
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CPU_K6_2,
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CPU_K6_2C,
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CPU_K6_3,
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CPU_K6_2P,
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CPU_K6_3P,
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CPU_CYRIX3S,
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CPU_PENTIUMPRO, /* 686 class CPUs */
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CPU_PENTIUM2,
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CPU_PENTIUM2D
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};
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enum {
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CPU_PKG_8088 = (1 << 0),
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CPU_PKG_8088_EUROPC = (1 << 1),
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CPU_PKG_8086 = (1 << 2),
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CPU_PKG_286 = (1 << 3),
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CPU_PKG_386SX = (1 << 4),
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CPU_PKG_386DX = (1 << 5),
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CPU_PKG_M6117 = (1 << 6),
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CPU_PKG_386SLC_IBM = (1 << 7),
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CPU_PKG_486SLC = (1 << 8),
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CPU_PKG_486SLC_IBM = (1 << 9),
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CPU_PKG_486BL = (1 << 10),
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CPU_PKG_486DLC = (1 << 11),
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CPU_PKG_SOCKET1 = (1 << 12),
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CPU_PKG_SOCKET3 = (1 << 13),
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CPU_PKG_SOCKET3_PC330 = (1 << 14),
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CPU_PKG_STPC = (1 << 15),
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CPU_PKG_SOCKET4 = (1 << 16),
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CPU_PKG_SOCKET5_7 = (1 << 17),
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CPU_PKG_SOCKET8 = (1 << 18),
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CPU_PKG_SLOT1 = (1 << 19),
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CPU_PKG_SLOT2 = (1 << 20),
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CPU_PKG_SOCKET370 = (1 << 21),
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CPU_PKG_EBGA368 = (1 << 22)
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};
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#define MANU_INTEL 0
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#define MANU_AMD 1
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#define MANU_CYRIX 2
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#define MANU_IDT 3
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#define MANU_NEC 4
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#define CPU_SUPPORTS_DYNAREC 1
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#define CPU_REQUIRES_DYNAREC 2
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#define CPU_ALTERNATE_XTAL 4
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#define CPU_FIXED_MULTIPLIER 8
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#if (defined __amd64__ || defined _M_X64)
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#define LOOKUP_INV -1LL
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#else
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#define LOOKUP_INV -1
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#endif
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typedef struct {
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const char *name;
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const char *internal_name;
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const int type;
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} FPU;
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typedef struct {
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const char *name;
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uint64_t cpu_type;
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const FPU *fpus;
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int rspeed;
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double multi;
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uint16_t voltage;
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uint32_t edx_reset;
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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uint8_t cpu_flags;
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int8_t mem_read_cycles, mem_write_cycles;
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int8_t cache_read_cycles, cache_write_cycles;
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int8_t atclk_div;
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} CPU;
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typedef struct {
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const uint32_t package;
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const char *manufacturer;
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const char *name;
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const char *internal_name;
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const CPU *cpus;
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} cpu_family_t;
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typedef struct {
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const char *family;
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const int rspeed;
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const double multi;
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} cpu_legacy_table_t;
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typedef struct {
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const char *machine;
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const cpu_legacy_table_t **tables;
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} cpu_legacy_machine_t;
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#define C_FLAG 0x0001
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#define P_FLAG 0x0004
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#define A_FLAG 0x0010
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#define Z_FLAG 0x0040
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#define N_FLAG 0x0080
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#define T_FLAG 0x0100
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#define I_FLAG 0x0200
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#define D_FLAG 0x0400
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#define V_FLAG 0x0800
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#define NT_FLAG 0x4000
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#define RF_FLAG 0x0001 /* in EFLAGS */
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#define VM_FLAG 0x0002 /* in EFLAGS */
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#define VIF_FLAG 0x0008 /* in EFLAGS */
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#define VIP_FLAG 0x0010 /* in EFLAGS */
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#define VID_FLAG 0x0020 /* in EFLAGS */
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#define WP_FLAG 0x10000 /* in CR0 */
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#define CR4_VME (1 << 0)
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#define CR4_PVI (1 << 1)
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#define CR4_PSE (1 << 4)
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#define CR4_PAE (1 << 5)
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#define CPL ((cpu_state.seg_cs.access>>5)&3)
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#define IOPL ((cpu_state.flags>>12)&3)
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#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
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typedef union {
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uint32_t l;
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uint16_t w;
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struct {
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uint8_t l,
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h;
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} b;
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} x86reg;
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typedef struct {
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uint8_t access, ar_high;
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int8_t checked; /*Non-zero if selector is known to be valid*/
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uint16_t seg;
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uint32_t base, limit,
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limit_low, limit_high;
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} x86seg;
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typedef union {
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uint64_t q;
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int64_t sq;
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uint32_t l[2];
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int32_t sl[2];
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uint16_t w[4];
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int16_t sw[4];
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uint8_t b[8];
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int8_t sb[8];
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float f[2];
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} MMX_REG;
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typedef struct {
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/* IDT WinChip and WinChip 2 MSR's */
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uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
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uint32_t cesr; /* 0x00000011 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx17; /* 0x00000017 - Only on Pentium II Deschutes */
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uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
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uint64_t ecx79; /* 0x00000079 */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t ecx83; /* 0x00000083 - AMD K5 and K6 MSR's. */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx8x[4]; /* 0x00000088 - 0x0000008b */
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uint64_t ia32_pmc[8]; /* 0x000000c1 - 0x000000c8 */
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uint64_t mtrr_cap; /* 0x000000fe */
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/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx116; /* 0x00000116 */
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uint64_t ecx11x[4]; /* 0x00000118 - 0x0000011b */
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uint64_t ecx11e; /* 0x0000011e */
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/* Pentium II Klamath and Pentium II Deschutes MSR's */
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uint16_t sysenter_cs; /* 0x00000174 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_esp; /* 0x00000175 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_eip; /* 0x00000176 - SYSENTER/SYSEXIT MSR's */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
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uint64_t ecx1e0; /* 0x000001e0 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f */
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uint64_t mtrr_physmask[8]; /* 0x00000200 - 0x0000020f (ECX & 1) */
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uint64_t mtrr_fix64k_8000; /* 0x00000250 */
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uint64_t mtrr_fix16k_8000; /* 0x00000258 */
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uint64_t mtrr_fix16k_a000; /* 0x00000259 */
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uint64_t mtrr_fix4k[8]; /* 0x00000268 - 0x0000026f */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t pat; /* 0x00000277 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_deftype; /* 0x000002ff */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx404; /* 0x00000404 - Model Identification MSR's used by some Acer BIOSes */
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uint64_t ecx408; /* 0x00000408 */
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uint64_t ecx40c; /* 0x0000040c */
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uint64_t ecx410; /* 0x00000410 */
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uint64_t ecx570; /* 0x00000570 */
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/* IBM 386SLC, 486SLC, and 486BL MSR's */
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uint64_t ibm_por; /* 0x00001000 - Processor Operation Register */
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uint64_t ibm_crcr; /* 0x00001001 - Cache Region Control Register */
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/* IBM 486SLC and 486BL MSR's */
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uint64_t ibm_por2; /* 0x00001002 - Processor Operation Register */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx1002ff; /* 0x001002ff - MSR used by some Intel AMI boards */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_efer; /* 0xc0000080 */
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/* AMD K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t star; /* 0xc0000081 */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_whcr; /* 0xc0000082 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_uwccr; /* 0xc0000085 */
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/* AMD K6-2P and K6-3P MSR's */
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uint64_t amd_epmr; /* 0xc0000086 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
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/* K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_l2aar; /* 0xc0000089 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecxf0f00250; /* 0xf0f00250 - Some weird long MSR's used by i686 AMI & some Phoenix BIOSes */
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uint64_t ecxf0f00258; /* 0xf0f00258 */
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uint64_t ecxf0f00259; /* 0xf0f00259 */
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} msr_t;
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typedef struct {
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x86reg regs[8];
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uint8_t tag[8];
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x86seg *ea_seg;
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uint32_t eaaddr;
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int flags_op;
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uint32_t flags_res,
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flags_op1, flags_op2;
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uint32_t pc,
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oldpc, op32;
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int TOP;
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union {
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struct {
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int8_t rm,
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mod,
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reg;
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} rm_mod_reg;
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int32_t rm_mod_reg_data;
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} rm_data;
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uint8_t ssegs, ismmx,
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abrt, pad;
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int _cycles;
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uint16_t npxs, npxc;
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double ST[8];
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uint16_t MM_w4[8];
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MMX_REG MM[8];
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uint16_t old_npxc, new_npxc;
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#ifdef USE_NEW_DYNAREC
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uint32_t old_fp_control, new_fp_control;
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#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
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uint16_t old_fp_control2, new_fp_control2;
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#endif
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#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
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uint32_t trunc_fp_control;
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#endif
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#endif
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x86seg seg_cs, seg_ds, seg_es, seg_ss,
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seg_fs, seg_gs;
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union {
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uint32_t l;
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uint16_t w;
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} CR0;
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uint16_t flags, eflags;
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} cpu_state_t;
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/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
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to be valid*/
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#define CPU_STATUS_USE32 (1 << 0)
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#define CPU_STATUS_STACK32 (1 << 1)
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#define CPU_STATUS_PMODE (1 << 2)
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#define CPU_STATUS_V86 (1 << 3)
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#define CPU_STATUS_SMM (1 << 4)
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#define CPU_STATUS_FLAGS 0xffff
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/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status.
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Otherwise they are ignored*/
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#ifdef USE_NEW_DYNAREC
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#define CPU_STATUS_NOTFLATDS (1 << 8)
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#define CPU_STATUS_NOTFLATSS (1 << 9)
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#define CPU_STATUS_MASK 0xff00
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#else
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#define CPU_STATUS_NOTFLATDS (1 << 16)
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#define CPU_STATUS_NOTFLATSS (1 << 17)
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#define CPU_STATUS_MASK 0xffff0000
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#endif
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#ifdef _MSC_VER
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# define COMPILE_TIME_ASSERT(expr) /*nada*/
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#else
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# ifdef EXTREME_DEBUG
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# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0];
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# else
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# define COMPILE_TIME_ASSERT(expr) /*nada*/
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# endif
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#endif
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COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
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#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128))
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#define EAX cpu_state.regs[0].l
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#define AX cpu_state.regs[0].w
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#define AL cpu_state.regs[0].b.l
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#define AH cpu_state.regs[0].b.h
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#define ECX cpu_state.regs[1].l
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#define CX cpu_state.regs[1].w
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#define CL cpu_state.regs[1].b.l
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#define CH cpu_state.regs[1].b.h
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#define EDX cpu_state.regs[2].l
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#define DX cpu_state.regs[2].w
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#define DL cpu_state.regs[2].b.l
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#define DH cpu_state.regs[2].b.h
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#define EBX cpu_state.regs[3].l
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#define BX cpu_state.regs[3].w
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#define BL cpu_state.regs[3].b.l
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#define BH cpu_state.regs[3].b.h
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#define ESP cpu_state.regs[4].l
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#define EBP cpu_state.regs[5].l
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#define ESI cpu_state.regs[6].l
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#define EDI cpu_state.regs[7].l
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#define SP cpu_state.regs[4].w
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#define BP cpu_state.regs[5].w
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#define SI cpu_state.regs[6].w
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#define DI cpu_state.regs[7].w
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#define cycles cpu_state._cycles
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#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm
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#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod
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#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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#define CR4_MCE (1 << 6)
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#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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/* Global variables. */
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extern cpu_state_t cpu_state;
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extern const cpu_family_t cpu_families[];
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extern const cpu_legacy_machine_t cpu_legacy_table[];
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extern cpu_family_t *cpu_f;
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extern CPU *cpu_s;
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extern int cpu_override;
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extern int cpu_isintel;
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extern int cpu_iscyrix;
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extern int cpu_16bitbus, cpu_64bitbus;
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extern int cpu_busspeed, cpu_pci_speed;
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extern int cpu_multi;
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extern double cpu_dmulti;
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extern double fpu_multi;
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extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
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penalties when crossing 8-byte boundaries*/
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extern int is8086, is286, is386, is486;
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extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
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extern int hascache;
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extern int isibm486;
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extern int is_rapidcad;
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extern int hasfpu;
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#define CPU_FEATURE_RDTSC (1 << 0)
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#define CPU_FEATURE_MSR (1 << 1)
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#define CPU_FEATURE_MMX (1 << 2)
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#define CPU_FEATURE_CR4 (1 << 3)
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#define CPU_FEATURE_VME (1 << 4)
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#define CPU_FEATURE_CX8 (1 << 5)
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#define CPU_FEATURE_3DNOW (1 << 6)
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extern uint32_t cpu_features;
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extern int in_smm, smi_line, smi_latched, smm_in_hlt;
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extern int smi_block;
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extern uint32_t smbase;
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#ifdef USE_NEW_DYNAREC
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extern uint16_t cpu_cur_status;
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#else
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extern uint32_t cpu_cur_status;
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#endif
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extern uint64_t cpu_CR4_mask;
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extern uint64_t tsc;
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extern msr_t msr;
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extern uint8_t opcode;
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extern int cgate16;
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extern int cpl_override;
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extern int CPUID;
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extern uint64_t xt_cpu_multi;
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extern int isa_cycles, cpu_inited;
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extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
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extern uint32_t pccache;
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extern uint8_t *pccache2;
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extern double bus_timing, isa_timing, pci_timing, agp_timing;
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extern uint64_t pmc[2];
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extern uint16_t temp_seg_data[4];
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extern uint16_t cs_msr;
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extern uint32_t esp_msr;
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extern uint32_t eip_msr;
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/* For the AMD K6. */
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extern uint64_t amd_efer, star;
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#define FPU_CW_Reserved_Bits (0xe0c0)
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#define cr0 cpu_state.CR0.l
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#define msw cpu_state.CR0.w
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extern uint32_t cr2, cr3, cr4;
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extern uint32_t dr[8];
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/*Segments -
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_cs,_ds,_es,_ss are the segment structures
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CS,DS,ES,SS is the 16-bit data
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cs,ds,es,ss are defines to the bases*/
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extern x86seg gdt,ldt,idt,tr;
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extern x86seg _oldds;
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#define CS cpu_state.seg_cs.seg
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#define DS cpu_state.seg_ds.seg
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#define ES cpu_state.seg_es.seg
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#define SS cpu_state.seg_ss.seg
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#define FS cpu_state.seg_fs.seg
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#define GS cpu_state.seg_gs.seg
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#define cs cpu_state.seg_cs.base
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#define ds cpu_state.seg_ds.base
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#define es cpu_state.seg_es.base
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#define ss cpu_state.seg_ss.base
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#define fs_seg cpu_state.seg_fs.base
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#define gs cpu_state.seg_gs.base
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#define ISA_CYCLES(x) (x * isa_cycles)
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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extern int cpu_isa_speed, cpu_pci_speed, cpu_agp_speed;
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|
|
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extern int timing_rr;
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extern int timing_mr, timing_mrl;
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extern int timing_rm, timing_rml;
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extern int timing_mm, timing_mml;
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extern int timing_bt, timing_bnt;
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extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
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extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
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extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
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extern int timing_call_pm_gate, timing_call_pm_gate_inner;
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extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
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|
extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
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|
extern int timing_misaligned;
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|
|
|
extern int in_sys, unmask_a20_in_smm;
|
|
extern int cycles_main;
|
|
extern uint32_t old_rammask;
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|
|
|
#ifdef USE_ACYCS
|
|
extern int acycs;
|
|
#endif
|
|
extern int pic_pending, is_vpc;
|
|
extern int soft_reset_mask, alt_access;
|
|
extern int cpu_end_block_after_ins;
|
|
|
|
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
|
|
extern uint32_t cpu_fast_off_flags;
|
|
|
|
|
|
/* Functions. */
|
|
extern int cpu_has_feature(int feature);
|
|
|
|
#ifdef USE_NEW_DYNAREC
|
|
extern void loadseg_dynarec(uint16_t seg, x86seg *s);
|
|
extern int loadseg(uint16_t seg, x86seg *s);
|
|
extern void loadcs(uint16_t seg);
|
|
#else
|
|
extern void loadseg(uint16_t seg, x86seg *s);
|
|
extern void loadcs(uint16_t seg);
|
|
#endif
|
|
|
|
extern char *cpu_current_pc(char *bufp);
|
|
|
|
extern void cpu_update_waitstates(void);
|
|
extern void cpu_set(void);
|
|
extern void cpu_close(void);
|
|
extern void cpu_set_isa_speed(int speed);
|
|
extern void cpu_set_pci_speed(int speed);
|
|
extern void cpu_set_isa_pci_div(int div);
|
|
extern void cpu_set_agp_speed(int speed);
|
|
|
|
extern void cpu_CPUID(void);
|
|
extern void cpu_RDMSR(void);
|
|
extern void cpu_WRMSR(void);
|
|
|
|
extern int checkio(uint32_t port);
|
|
extern void codegen_block_end(void);
|
|
extern void codegen_reset(void);
|
|
extern void cpu_set_edx(void);
|
|
extern int divl(uint32_t val);
|
|
extern void execx86(int cycs);
|
|
extern void enter_smm(int in_hlt);
|
|
extern void enter_smm_check(int in_hlt);
|
|
extern void leave_smm(void);
|
|
extern void exec386(int cycs);
|
|
extern void exec386_dynarec(int cycs);
|
|
extern int idivl(int32_t val);
|
|
#ifdef USE_NEW_DYNAREC
|
|
extern void loadcscall(uint16_t seg, uint32_t old_pc);
|
|
extern void loadcsjmp(uint16_t seg, uint32_t old_pc);
|
|
extern void pmodeint(int num, int soft);
|
|
extern void pmoderetf(int is32, uint16_t off);
|
|
extern void pmodeiret(int is32);
|
|
#else
|
|
extern void loadcscall(uint16_t seg);
|
|
extern void loadcsjmp(uint16_t seg, uint32_t old_pc);
|
|
extern void pmodeint(int num, int soft);
|
|
extern void pmoderetf(int is32, uint16_t off);
|
|
extern void pmodeiret(int is32);
|
|
#endif
|
|
extern void resetmcr(void);
|
|
extern void resetx86(void);
|
|
extern void refreshread(void);
|
|
extern void resetreadlookup(void);
|
|
extern void softresetx86(void);
|
|
extern void x86_int(int num);
|
|
extern void x86_int_sw(int num);
|
|
extern int x86_int_sw_rm(int num);
|
|
extern void x86gpf(char *s, uint16_t error);
|
|
extern void x86np(char *s, uint16_t error);
|
|
extern void x86ss(char *s, uint16_t error);
|
|
extern void x86ts(char *s, uint16_t error);
|
|
|
|
#ifdef ENABLE_808X_LOG
|
|
extern void dumpregs(int __force);
|
|
extern void x87_dumpregs(void);
|
|
extern void x87_reset(void);
|
|
#endif
|
|
|
|
extern int cpu_effective, cpu_alt_reset;
|
|
extern void cpu_dynamic_switch(int new_cpu);
|
|
|
|
extern void cpu_ven_reset(void);
|
|
extern void update_tsc(void);
|
|
|
|
extern int sysenter(uint32_t fetchdat);
|
|
extern int sysexit(uint32_t fetchdat);
|
|
extern int syscall_op(uint32_t fetchdat);
|
|
extern int sysret(uint32_t fetchdat);
|
|
|
|
extern cpu_family_t *cpu_get_family(const char *internal_name);
|
|
extern uint8_t cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine);
|
|
extern uint8_t cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine);
|
|
extern int fpu_get_type(const cpu_family_t *cpu_family, int cpu, const char *internal_name);
|
|
extern const char *fpu_get_internal_name(const cpu_family_t *cpu_family, int cpu, int type);
|
|
extern const char *fpu_get_name_from_index(const cpu_family_t *cpu_family, int cpu, int c);
|
|
extern int fpu_get_type_from_index(const cpu_family_t *cpu_family, int cpu, int c);
|
|
|
|
void cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg);
|
|
void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
|
|
|
|
#define SMHR_VALID (1 << 0)
|
|
#define SMHR_ADDR_MASK (0xfffffffc)
|
|
|
|
typedef struct
|
|
{
|
|
struct
|
|
{
|
|
uint32_t base;
|
|
uint64_t size;
|
|
} arr[8];
|
|
uint32_t smhr;
|
|
} cyrix_t;
|
|
|
|
|
|
extern uint32_t addr64, addr64_2;
|
|
extern uint32_t addr64a[8], addr64a_2[8];
|
|
|
|
extern int soft_reset_pci;
|
|
|
|
extern int reset_on_hlt, hlt_reset_pending;
|
|
|
|
extern cyrix_t cyrix;
|
|
|
|
extern void (*cpu_exec)(int cycs);
|
|
extern uint8_t do_translate, do_translate2;
|
|
|
|
extern void reset_808x(int hard);
|
|
|
|
#endif /*EMU_CPU_H*/
|