55b6f1b802
Floppy disk controller is now COMPLETELY reset on hard reset; NukedOPL is now optional (but enabled by default) so people on older hardware can gain a few % of performance by going back to DOSBox OPL; *.CPP files now get all the correct optimization flags applied; Added NEC PowerMate V emulation - you can get into CMOS SETUP but it hangs before booting, and PCI graphics card don't work (yet).
169 lines
5.6 KiB
C
169 lines
5.6 KiB
C
/* Copyright holders: Sarah Walker, Tenshi
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see COPYING for more details
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*/
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#include "ibm.h"
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#include "disc.h"
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#include "fdc.h"
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#include "fdd.h"
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#include "io.h"
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#include "lpt.h"
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#include "serial.h"
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#include "fdc37c665.h"
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static uint8_t fdc37c665_lock[2];
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static int fdc37c665_curreg;
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static uint8_t fdc37c665_regs[16];
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static void write_lock(uint8_t val)
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{
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if (val == 0x55 && fdc37c665_lock[1] == 0x55)
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fdc_3f1_enable(0);
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if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55 && val != 0x55)
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fdc_3f1_enable(1);
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fdc37c665_lock[0] = fdc37c665_lock[1];
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fdc37c665_lock[1] = val;
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}
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void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
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{
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// pclog("Write SuperIO %04x %02x\n", port, val);
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if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
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{
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if (port == 0x3f0)
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{
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if (val == 0xaa)
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write_lock(val);
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else
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fdc37c665_curreg = val & 0xf;
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}
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else
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{
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uint16_t com3_addr, com4_addr;
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fdc37c665_regs[fdc37c665_curreg] = val;
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// pclog("Write superIO %02x %02x %04x(%08x):%08x\n", fdc37c665_curreg, val, CS, cs, pc);
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switch (fdc37c665_regs[1] & 0x60)
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{
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case 0x00:
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com3_addr = 0x338;
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com4_addr = 0x238;
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break;
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case 0x20:
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com3_addr = 0x3e8;
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com4_addr = 0x2e8;
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break;
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case 0x40:
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com3_addr = 0x3e8;
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com4_addr = 0x2e0;
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break;
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case 0x60:
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com3_addr = 0x220;
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com4_addr = 0x228;
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break;
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}
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if (!(fdc37c665_regs[2] & 4))
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serial1_remove();
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else switch (fdc37c665_regs[2] & 3)
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{
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case 0:
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serial1_set(0x3f8, 4);
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break;
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case 1:
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serial1_set(0x2f8, 4);
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break;
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case 2:
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serial1_set(com3_addr, 4);
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break;
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case 3:
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serial1_set(com4_addr, 4);
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break;
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}
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if (!(fdc37c665_regs[2] & 0x40))
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serial2_remove();
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else switch (fdc37c665_regs[2] & 0x30)
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{
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case 0x00:
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serial2_set(0x3f8, 3);
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break;
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case 0x10:
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serial2_set(0x2f8, 3);
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break;
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case 0x20:
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serial2_set(com3_addr, 3);
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break;
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case 0x30:
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serial2_set(com4_addr, 3);
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break;
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}
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lpt1_remove();
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lpt2_remove();
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switch (fdc37c665_regs[1] & 3)
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{
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case 1:
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lpt1_init(0x3bc);
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break;
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case 2:
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lpt1_init(0x378);
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break;
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case 3:
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lpt1_init(0x278);
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break;
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}
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fdc_update_enh_mode((fdc37c665_regs[3] & 2) ? 1 : 0);
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fdc_update_densel_force((fdc37c665_regs[5] & 0x18) >> 3);
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fdd_swap = ((fdc37c665_regs[5] & 0x20) >> 5);
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}
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}
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else
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{
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if (port == 0x3f0)
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write_lock(val);
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}
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}
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uint8_t fdc37c665_read(uint16_t port, void *priv)
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{
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// pclog("Read SuperIO %04x %02x\n", port, fdc37c665_curreg);
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if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
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{
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if (port == 0x3f1)
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return fdc37c665_regs[fdc37c665_curreg];
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}
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return 0xff;
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}
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void fdc37c665_reset(void)
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{
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fdc_update_is_nsc(0);
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memset(fdc37c665_lock, 0, 2);
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memset(fdc37c665_regs, 0, 16);
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fdc37c665_regs[0x0] = 0x3b;
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fdc37c665_regs[0x1] = 0x9f;
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fdc37c665_regs[0x2] = 0xdc;
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fdc37c665_regs[0x3] = 0x78;
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fdc37c665_regs[0x6] = 0xff;
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fdc37c665_regs[0xd] = 0x65;
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fdc37c665_regs[0xe] = 0x01;
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fdc_update_densel_polarity(1);
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fdc_update_densel_force(0);
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fdd_swap = 0;
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}
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void fdc37c665_init()
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{
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io_sethandler(0x03f0, 0x0002, fdc37c665_read, NULL, NULL, fdc37c665_write, NULL, NULL, NULL);
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fdc37c665_reset();
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pci_reset_handler.super_io_reset = fdc37c665_reset;
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}
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