dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
203 lines
4.9 KiB
C
203 lines
4.9 KiB
C
static int opCMC(uint32_t fetchdat)
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{
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flags_rebuild();
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flags ^= C_FLAG;
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opCLC(uint32_t fetchdat)
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{
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flags_rebuild();
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flags &= ~C_FLAG;
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opCLD(uint32_t fetchdat)
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{
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flags &= ~D_FLAG;
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opCLI(uint32_t fetchdat)
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{
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if (!IOPLp)
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{
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x86gpf(NULL,0);
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return 1;
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}
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else
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flags &= ~I_FLAG;
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CLOCK_CYCLES(3);
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PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opSTC(uint32_t fetchdat)
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{
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flags_rebuild();
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flags |= C_FLAG;
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opSTD(uint32_t fetchdat)
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{
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flags |= D_FLAG;
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opSTI(uint32_t fetchdat)
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{
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if (!IOPLp)
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{
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x86gpf(NULL,0);
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return 1;
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}
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else
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flags |= I_FLAG;
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CPU_BLOCK_END();
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CLOCK_CYCLES(2);
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PREFETCH_RUN(2, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opSAHF(uint32_t fetchdat)
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{
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flags_rebuild();
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flags = (flags & 0xff00) | (AH & 0xd5) | 2;
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CLOCK_CYCLES(3);
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PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
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codegen_flags_changed = 0;
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return 0;
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}
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static int opLAHF(uint32_t fetchdat)
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{
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flags_rebuild();
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AH = flags & 0xff;
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CLOCK_CYCLES(3);
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PREFETCH_RUN(3, 1, -1, 0,0,0,0, 0);
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return 0;
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}
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static int opPUSHF(uint32_t fetchdat)
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{
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if ((eflags & VM_FLAG) && (IOPL < 3))
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{
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x86gpf(NULL,0);
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return 1;
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}
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flags_rebuild();
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PUSH_W(flags);
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
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return cpu_state.abrt;
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}
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static int opPUSHFD(uint32_t fetchdat)
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{
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uint16_t tempw;
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if ((eflags & VM_FLAG) && (IOPL < 3))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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if (CPUID) tempw = eflags & 0x24;
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else tempw = eflags & 4;
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flags_rebuild();
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PUSH_L(flags | (tempw << 16));
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0,0,0,1, 0);
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return cpu_state.abrt;
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}
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static int opPOPF_286(uint32_t fetchdat)
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{
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uint16_t tempw;
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if ((eflags & VM_FLAG) && (IOPL < 3))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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tempw = POP_W(); if (cpu_state.abrt) return 1;
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if (!(msw & 1)) flags = (flags & 0x7000) | (tempw & 0x0fd5) | 2;
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else if (!(CPL)) flags = (tempw & 0x7fd5) | 2;
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else if (IOPLp) flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
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else flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
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flags_extract();
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
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codegen_flags_changed = 0;
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return 0;
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}
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static int opPOPF(uint32_t fetchdat)
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{
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uint16_t tempw;
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if ((eflags & VM_FLAG) && (IOPL < 3))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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tempw = POP_W(); if (cpu_state.abrt) return 1;
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if (!(CPL) || !(msw & 1)) flags = (tempw & 0x7fd5) | 2;
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else if (IOPLp) flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
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else flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
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flags_extract();
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1,0,0,0, 0);
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codegen_flags_changed = 0;
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return 0;
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}
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static int opPOPFD(uint32_t fetchdat)
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{
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uint32_t templ;
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if ((eflags & VM_FLAG) && (IOPL < 3))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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templ = POP_L(); if (cpu_state.abrt) return 1;
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if (!(CPL) || !(msw & 1)) flags = (templ & 0x7fd5) | 2;
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else if (IOPLp) flags = (flags & 0x3000) | (templ & 0x4fd5) | 2;
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else flags = (flags & 0x3200) | (templ & 0x4dd5) | 2;
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templ &= is486 ? 0x240000 : 0;
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templ |= ((eflags&3) << 16);
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if (CPUID) eflags = (templ >> 16) & 0x27;
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else if (is486) eflags = (templ >> 16) & 7;
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else eflags = (templ >> 16) & 3;
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flags_extract();
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 0,1,0,0, 0);
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codegen_flags_changed = 0;
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return 0;
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}
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