dc46480aa4
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
297 lines
8.5 KiB
C
297 lines
8.5 KiB
C
static int opMOV_r_CRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from CRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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cpu_state.regs[cpu_rm].l = cr0;
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if (is486)
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cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
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break;
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case 2:
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cpu_state.regs[cpu_rm].l = cr2;
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break;
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case 3:
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cpu_state.regs[cpu_rm].l = cr3;
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break;
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case 4:
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if (cpu_hasCR4)
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{
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cpu_state.regs[cpu_rm].l = cr4;
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break;
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}
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default:
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pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_CRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from CRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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cpu_state.regs[cpu_rm].l = cr0;
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if (is486)
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cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
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break;
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case 2:
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cpu_state.regs[cpu_rm].l = cr2;
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break;
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case 3:
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cpu_state.regs[cpu_rm].l = cr3;
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break;
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case 4:
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if (cpu_hasCR4)
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{
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cpu_state.regs[cpu_rm].l = cr4;
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break;
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}
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default:
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pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_r_DRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from DRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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cpu_state.regs[cpu_rm].l = dr[cpu_reg];
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_DRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from DRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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cpu_state.regs[cpu_rm].l = dr[cpu_reg];
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_CRx_r_a16(uint32_t fetchdat)
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{
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uint32_t old_cr0 = cr0;
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load CRx\n");
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x86gpf(NULL,0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
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flushmmucache();
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cr0 = cpu_state.regs[cpu_rm].l;
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if (cpu_16bitbus)
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cr0 |= 0x10;
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if (!(cr0 & 0x80000000))
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mmu_perm=4;
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if (is486 && !(cr0 & (1 << 30)))
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cpu_cache_int_enabled = 1;
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else
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cpu_cache_int_enabled = 0;
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if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
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cpu_update_waitstates();
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break;
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case 2:
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cr2 = cpu_state.regs[cpu_rm].l;
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break;
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case 3:
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cr3 = cpu_state.regs[cpu_rm].l;
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flushmmucache();
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break;
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case 4:
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if (cpu_hasCR4)
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{
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cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
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break;
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}
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default:
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pclog("Bad load CR%i\n", cpu_reg);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(10);
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PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_CRx_r_a32(uint32_t fetchdat)
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{
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uint32_t old_cr0 = cr0;
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load CRx\n");
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x86gpf(NULL,0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
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flushmmucache();
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cr0 = cpu_state.regs[cpu_rm].l;
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if (cpu_16bitbus)
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cr0 |= 0x10;
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if (!(cr0 & 0x80000000))
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mmu_perm=4;
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if (is486 && !(cr0 & (1 << 30)))
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cpu_cache_int_enabled = 1;
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else
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cpu_cache_int_enabled = 0;
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if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
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cpu_update_waitstates();
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break;
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case 2:
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cr2 = cpu_state.regs[cpu_rm].l;
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break;
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case 3:
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cr3 = cpu_state.regs[cpu_rm].l;
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flushmmucache();
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break;
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case 4:
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if (cpu_hasCR4)
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{
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cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
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break;
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}
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default:
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pclog("Bad load CR%i\n", cpu_reg);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(10);
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PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_DRx_r_a16(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load DRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DRx_r_a32(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load DRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_r_TRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from TRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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cpu_state.regs[cpu_rm].l = 0;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_TRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load from TRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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cpu_state.regs[cpu_rm].l = 0;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_TRx_r_a16(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load TRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_TRx_r_a32(uint32_t fetchdat)
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{
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if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
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{
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pclog("Can't load TRx\n");
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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