0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
268 lines
9.3 KiB
C
268 lines
9.3 KiB
C
#ifdef USE_NEW_DYNAREC
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#define CPU_SET_OXPC
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#else
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#define CPU_SET_OXPC oxpc = cpu_state.pc;
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#endif
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#define RETF_a16(stack_offset) \
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if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
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{ \
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pmoderetf(0, stack_offset); \
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return 1; \
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} \
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CPU_SET_OXPC \
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if (stack32) \
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{ \
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cpu_state.pc = readmemw(ss, ESP); \
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loadcs(readmemw(ss, ESP + 2)); \
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} \
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else \
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{ \
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cpu_state.pc = readmemw(ss, SP); \
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loadcs(readmemw(ss, SP + 2)); \
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} \
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if (cpu_state.abrt) return 1; \
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if (stack32) ESP += 4 + stack_offset; \
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else SP += 4 + stack_offset; \
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cycles -= timing_retf_rm;
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#define RETF_a32(stack_offset) \
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if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
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{ \
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pmoderetf(1, stack_offset); \
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return 1; \
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} \
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CPU_SET_OXPC \
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if (stack32) \
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{ \
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cpu_state.pc = readmeml(ss, ESP); \
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loadcs(readmeml(ss, ESP + 4) & 0xffff); \
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} \
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else \
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{ \
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cpu_state.pc = readmeml(ss, SP); \
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loadcs(readmeml(ss, SP + 4) & 0xffff); \
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} \
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if (cpu_state.abrt) return 1; \
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if (stack32) ESP += 8 + stack_offset; \
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else SP += 8 + stack_offset; \
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cycles -= timing_retf_rm;
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static int opRETF_a16(uint32_t fetchdat)
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{
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int cycles_old = cycles; UN_USED(cycles_old);
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CPU_BLOCK_END();
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RETF_a16(0);
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PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a32(uint32_t fetchdat)
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{
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int cycles_old = cycles; UN_USED(cycles_old);
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CPU_BLOCK_END();
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RETF_a32(0);
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PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,2,0,0, 1);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a16_imm(uint32_t fetchdat)
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{
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uint16_t offset = getwordf();
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int cycles_old = cycles; UN_USED(cycles_old);
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CPU_BLOCK_END();
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RETF_a16(offset);
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PREFETCH_RUN(cycles_old-cycles, 3, -1, 2,0,0,0, 0);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a32_imm(uint32_t fetchdat)
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{
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uint16_t offset = getwordf();
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int cycles_old = cycles; UN_USED(cycles_old);
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CPU_BLOCK_END();
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RETF_a32(offset);
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PREFETCH_RUN(cycles_old-cycles, 3, -1, 0,2,0,0, 1);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opIRET_286(uint32_t fetchdat)
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{
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int cycles_old = cycles; UN_USED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
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{
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x86gpf(NULL,0);
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return 1;
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}
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if (msw&1)
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{
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optype = IRET;
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pmodeiret(0);
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optype = 0;
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}
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else
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{
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uint16_t new_cs;
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CPU_SET_OXPC
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if (stack32)
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{
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cpu_state.pc = readmemw(ss, ESP);
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new_cs = readmemw(ss, ESP + 2);
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cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ESP + 4) & 0xffd5) | 2;
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ESP += 6;
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}
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else
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{
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cpu_state.pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ((SP + 4) & 0xffff)) & 0x0fd5) | 2;
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SP += 6;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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static int opIRET(uint32_t fetchdat)
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{
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int cycles_old = cycles; UN_USED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
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{
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if (cr4 & CR4_VME)
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{
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uint16_t new_pc, new_cs, new_flags;
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new_pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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new_flags = readmemw(ss, ((SP + 4) & 0xffff));
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if (cpu_state.abrt)
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return 1;
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if ((new_flags & T_FLAG) || ((new_flags & I_FLAG) && (cpu_state.eflags & VIP_FLAG)))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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SP += 6;
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if (new_flags & I_FLAG)
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cpu_state.eflags |= VIF_FLAG;
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else
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cpu_state.eflags &= ~VIF_FLAG;
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cpu_state.flags = (cpu_state.flags & 0x3300) | (new_flags & 0x4cd5) | 2;
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loadcs(new_cs);
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cpu_state.pc = new_pc;
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cycles -= timing_iret_rm;
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}
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else
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{
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x86gpf_expected(NULL,0);
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return 1;
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}
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}
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else
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{
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if (msw&1)
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{
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optype = IRET;
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pmodeiret(0);
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optype = 0;
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}
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else
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{
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uint16_t new_cs;
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CPU_SET_OXPC
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if (stack32)
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{
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cpu_state.pc = readmemw(ss, ESP);
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new_cs = readmemw(ss, ESP + 2);
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cpu_state.flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
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ESP += 6;
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}
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else
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{
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cpu_state.pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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cpu_state.flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
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SP += 6;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old-cycles, 1, -1, 2,0,0,0, 0);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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static int opIRETD(uint32_t fetchdat)
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{
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int cycles_old = cycles; UN_USED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3))
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{
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x86gpf_expected(NULL,0);
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return 1;
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}
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if (msw & 1)
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{
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optype = IRET;
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pmodeiret(1);
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optype = 0;
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}
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else
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{
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uint16_t new_cs;
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CPU_SET_OXPC
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if (stack32)
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{
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cpu_state.pc = readmeml(ss, ESP);
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new_cs = readmemw(ss, ESP + 4);
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cpu_state.flags = (readmemw(ss, ESP + 8) & 0xffd5) | 2;
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cpu_state.eflags = readmemw(ss, ESP + 10);
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ESP += 12;
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}
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else
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{
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cpu_state.pc = readmeml(ss, SP);
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new_cs = readmemw(ss, ((SP + 4) & 0xffff));
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cpu_state.flags = (readmemw(ss,(SP + 8) & 0xffff) & 0xffd5) | 2;
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cpu_state.eflags = readmemw(ss, (SP + 10) & 0xffff);
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SP += 12;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old-cycles, 1, -1, 0,2,0,0, 1);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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