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86Box/src/sio_acc3221.c
OBattler 552a87ea3d Added the IBM 5161 ISA expansion for PC and XT; 
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g  / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ACC 3221-SP Super I/O Chip.
*
* Version: @(#)sio_acc3221.c 1.0.0 2019/04/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
*
* Copyright 2019 Sarah Walker.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "io.h"
#include "timer.h"
#include "device.h"
#include "pci.h"
#include "lpt.h"
#include "serial.h"
#include "disk/hdc.h"
#include "disk/hdc_ide.h"
#include "floppy/fdd.h"
#include "floppy/fdc.h"
#include "sio.h"
typedef struct acc3221_t
{
int reg_idx;
uint8_t regs[256];
fdc_t * fdc;
serial_t * uart[2];
} acc3221_t;
/* Configuration Register Index, BE (R/W):
Bit Function
7 PIRQ 5 polarity.
1 = active high, default
0 = active low
6 PIRQ 7 polarity.
1 = active high, default
0 = active low
5 Primary Parallel Port Extended Mode
0 = Compatible mode, default
1 = Extended/Bidirectional mode.
4 Primary Parallel Port Disable
1 = Disable, 0 = Enable
Power Up Default is set by pin 120
(3221-DP)/pin 96 (3221-SP)
3 Primary Parallel Port Power Down
1 = Power Down, default = 0
2** Secondary Parallel Port Extended
Mode
0 = Compatible mode, default
1 = Extended/Bidirectional mode.
1** Secondary Parallel Port Disable
1 = Disable, 0 = Enable
Power Up Default is set by pin 77
(3221-DP)
0** Secondary Parallel Port Power Down
1 = Power Down
0 = Enable, default
Note: Power Up not applicable to 3221-EP. */
#define REG_BE_LPT1_DISABLE (3 << 3)
#define REG_BE_LPT2_DISABLE (3 << 0) /* 3221-DP/EP only */
/* Configuration Register Index, BF (R/W):
Bit Function
7-0 The 8 most significant address bits of
the primary parallel port (A9-2)
Default 9E (LPT2, at 278-27B) */
/* Configuration Register Index, DA (R/W)**:
Bit Function
7-0 The 8 most significant address bits of
the secondary parallel port (A9-2)
Default DE (LPT1, at 378-37B) */
/* Configuration Register Index, DB (R/W):
Bit Function
7 SIRQ4 polarity.
1 = active high; default
0 = active low
6 SIRQ3 polarity.
1 = active high; default
0 = active low
5 SXTAL clock off. 1 = SCLK off,
0 = SCKL on, default
4 Primary serial port disable
1 = Disable, 0 = Enable
Power Up default is set by pin 116
(3221-DP)/pin 93 (3221-SP)
3 Primary serial port power down
1 = Power down, 0 = Enable
Power Up default is set by pin 116
(3221-DP)/pin 93 (3221-SP)
2 Reserved
1 Secondary serial port disable
1 = Disable, 0 = Enable
Power Up default is set by pin 121
(3221-DP)/pin 97 (3221-SP)
0 Secondary serial port power down
1 = Power down, 0 = Enable
Power Up default is set by pin 121
(3221-DP)/pin 97 (3221-SP)
Note: Power Up not applicable to 3221-EP. */
#define REG_DB_SERIAL1_DISABLE (3 << 3)
#define REG_DB_SERIAL2_DISABLE (3 << 0)
/* Configuration Register Index, DC (R/W):
Bit Function
7-1 The MSB of the Primary Serial Port
Address (bits A9-3).
Default = 7F (COM1, at 3F8-3FF).
0 When this bit is set to 1, bit A2 of
primary parallel port is decoded.
Default is 0. */
/* Configuration Register Index, DD (R/W):
Bit Function
7-1 The MSB of the Secondary Serial Port
Address (bits A9-3).
Default = 5F (COM2, at 2F8-2FF).
0** When this bit is set to 1, bit A2 of
secondary parallel port is decoded.
Default is 0. */
/* Configuration Register Index, DE (R/W):
Bit Function
7-6 SIRQ3 source
b7 b6
0 0 Disabled, tri-stated
0 1 Disabled, tri-stated**
1 0 Primary serial port
1 1 Secondary serial port,
default
5-4 SIRQ4 source
b5 b4
0 0 Disabled, tri-stated
0 1 Disabled, tri-stated**
1 0 Primary serial port,
default
1 1 Secondary serial port
3-2** PIRQ7 source
b3 b2
0 0 Diabled, tri-stated,
default
0 1 Primary serial port
1 0 Primary parallel port
1 1 Secondary parallel
port
Note: Bits 3-2 are reserved in 3221-SP.
1-0 PIRQ5 source
b1 b0
0 0 Disabled, tri-stated
0 1 Secondary serial port
1 0 Primary parallel port,
default
1 1 Secondary parallel
port** */
#define REG_DE_SIRQ3_SOURCE (3 << 6)
#define REG_DE_SIRQ3_SERIAL1 (1 << 6)
#define REG_DE_SIRQ3_SERIAL2 (3 << 6)
#define REG_DE_SIRQ4_SOURCE (3 << 4)
#define REG_DE_SIRQ4_SERIAL1 (1 << 4)
#define REG_DE_SIRQ4_SERIAL2 (3 << 4)
#define REG_DE_PIRQ7_SOURCE (3 << 2)
#define REG_DE_PIRQ7_SERIAL1 (1 << 2)
#define REG_DE_PIRQ7_LPT1 (2 << 2)
#define REG_DE_PIRQ7_LPT2 (3 << 2)
#define REG_DE_PIRQ5_SOURCE (3 << 0)
#define REG_DE_PIRQ5_SERIAL2 (1 << 0)
#define REG_DE_PIRQ5_LPT1 (2 << 0)
#define REG_DE_PIRQ5_LPT2 (3 << 0)
/* Configuration Register Index, DF (R/W)**:
Bit Function
7-6 Reserved
5 RTC interface disable
1 = /RTCCS disabled
0 = /RTCCS enabled, default
4 Disable Modem Select
1 = Moden CS disabled, default
0 = Modem CS enabled
3-2
b3 b2
1 1 Reserved
1 0 Modem port address
= 3E8-3EF (default)
0 1 Modem port address:
2F8-2FF
0 0 Modem port address:
3F8-3FF
1-0
b1 b0
1 1 Reserved
1 0 Mode 2, EISA Mode
0 1 Mode 1, AT BUS,
0 0 Mode 0, Two parallel
ports, default */
/* Configuration Register Index, FA (R/W)**:
Bit Function
7 General purpose I/O register, Bit 7
6 General purpose I/O register, Bit 6
5 General purpose I/O register, Bit 5
4 General purpose I/O register, Bit 4
3 General purpose I/O register, Bit 3
2 General purpose I/O register, Bit 2
1 General purpose I/O register, Bit 1
0 General purpose I/O register, Bit 0 */
/* Configuration Register Index, FB (R/W)**:
Bit Function
7 Reserved
6** 0/2 EXG (Read Only)
In mode 1 and mode 2
operation, when the third
floppy drive is installed, pin
EXTFDD should be pulled
high to enable the third floppy
drive or be pulled low to
disable the third floppy drive.
1 = Third floppy drive enabled
0 = Third floppy drive disabled
5** EXTFDD (Read Only)
In mode 1 and mode 2
operation, when the third
floppy drive is installed and
pin 0/2 EXG is pulled high,
the third floppy drive becomes
the bootable drive (drive 0).
When pi 0/2 EXG is pulled low,
the third floppy drive acts as
drive 2.
1 = Third floppy drive as drive 0 (bootable)
0 = Third floppy drive as drive 2
4** MS
In mode 1 and mode 2, t his bit is to
control the output pin MS to support a
special 3 1/2", 1.2M drive. When this
bit is set to high (1), the MS pin sends
a low signal. When this bit is set to
low (0), the MS pin sends a high
signal to support a 3 1/2", 1.2M drive.
3 FDC, Clock disable
0 = enable, default
1 = disable
2 Reserved
1 FDC disable
0 = enable, 1= disable
Power Upd efault set by pin 117 (3221-
DP)/pin 94 (3221-SP)
0 FDC address
0 = Primary, default
1 = Secondary
Note: Bits 6-4 are reserved in 3221-SP. */
#define REG_FB_FDC_DISABLE (1 << 1)
/* Configuration Register Index, FB (R/W)**:
Bit Function
7** Disable general chip select 1
1 = disable, default
0 = enable
6** Disable general chip select 2
1 = disable, default
0 = enable
5** Enable SA2 decoding for general chip
select 1
1 = enable
0 = disable, default
4** Enable SA2 decoding for general chip
select 2
1 = enable
0 = disable, default
3 Reserved
2 IDE XT selected
0 = IDE AT interface, default
1 = IDE XT interface
1 IDE disable, 1 = IDE disable
0 = IDE enable
Power Up default set by pin 13 (3221-
DP)/pin 13 (3221-SP)
0 Secondary IDE
1 = secondary
0 = primary, default
Note: Bits 6-4 are reserved in 3221-SP. */
#define REG_FE_IDE_DISABLE (1 << 1)
static void
acc3221_lpt_handle(acc3221_t *dev)
{
lpt1_remove();
if (!(dev->regs[0xbe] & REG_BE_LPT1_DISABLE))
lpt1_init(dev->regs[0xbf] << 2);
}
static void
acc3221_serial1_handler(acc3221_t *dev)
{
uint16_t com_addr = 0;
serial_remove(dev->uart[0]);
if (!(dev->regs[0xdb] & REG_DB_SERIAL1_DISABLE)) {
com_addr = ((dev->regs[0xdc] & 0xfe) << 2);
if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL1)
serial_setup(dev->uart[0], com_addr, 3);
else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL1)
serial_setup(dev->uart[0], com_addr, 4);
}
}
static void
acc3221_serial2_handler(acc3221_t *dev)
{
uint16_t com_addr = 0;
serial_remove(dev->uart[1]);
if (!(dev->regs[0xdb] & REG_DB_SERIAL2_DISABLE)) {
com_addr = ((dev->regs[0xdd] & 0xfe) << 2);
if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL2)
serial_setup(dev->uart[1], com_addr, 3);
else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL2)
serial_setup(dev->uart[1], com_addr, 4);
else if ((dev->regs[0xde] & REG_DE_PIRQ5_SOURCE) == REG_DE_PIRQ5_SERIAL2)
serial_setup(dev->uart[1], com_addr, 5);
}
}
static void
acc3221_write(uint16_t addr, uint8_t val, void *p)
{
acc3221_t *dev = (acc3221_t *)p;
uint8_t old;
if (!(addr & 1))
dev->reg_idx = val;
else {
old = dev->regs[dev->reg_idx];
dev->regs[dev->reg_idx] = val;
switch (dev->reg_idx) {
case 0xbe:
if ((old ^ val) & REG_BE_LPT1_DISABLE)
acc3221_lpt_handle(dev);
break;
case 0xbf:
if (old != val)
acc3221_lpt_handle(dev);
break;
case 0xdb:
if ((old ^ val) & REG_DB_SERIAL2_DISABLE)
acc3221_serial2_handler(dev);
if ((old ^ val) & REG_DB_SERIAL1_DISABLE)
acc3221_serial1_handler(dev);
break;
case 0xdc:
if (old != val)
acc3221_serial1_handler(dev);
break;
case 0xdd:
if (old != val)
acc3221_serial2_handler(dev);
break;
case 0xde:
if ((old ^ val) & (REG_DE_SIRQ3_SOURCE | REG_DE_SIRQ4_SOURCE)) {
acc3221_serial2_handler(dev);
acc3221_serial1_handler(dev);
}
break;
case 0xfb:
if ((old ^ val) & REG_FB_FDC_DISABLE) {
fdc_remove(dev->fdc);
if (!(dev->regs[0xfb] & REG_FB_FDC_DISABLE))
fdc_set_base(dev->fdc, 0x03f0);
}
break;
case 0xfe:
if ((old ^ val) & REG_FE_IDE_DISABLE) {
ide_pri_disable();
if (!(dev->regs[0xfe] & REG_FE_IDE_DISABLE))
ide_pri_enable();
}
break;
}
}
}
static uint8_t
acc3221_read(uint16_t addr, void *p)
{
acc3221_t *dev = (acc3221_t *)p;
if (!(addr & 1))
return dev->reg_idx;
if (dev->reg_idx < 0xbc)
return 0xff;
return dev->regs[dev->reg_idx];
}
static void
acc3221_reset(acc3221_t *dev)
{
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
lpt1_remove();
lpt1_init(0x378);
lpt1_irq(7);
fdc_reset(dev->fdc);
}
static void
acc3221_close(void *priv)
{
acc3221_t *dev = (acc3221_t *) priv;
free(dev);
}
static void *
acc3221_init(const device_t *info)
{
acc3221_t *dev = (acc3221_t *) malloc(sizeof(acc3221_t));
memset(dev, 0, sizeof(acc3221_t));
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
io_sethandler(0x00f2, 0x0002, acc3221_read, NULL, NULL, acc3221_write, NULL, NULL, dev);
acc3221_reset(dev);
return dev;
}
const device_t acc3221_device = {
"ACC 3221-SP Super I/O",
0,
0,
acc3221_init, acc3221_close, NULL,
NULL, NULL, NULL,
NULL
};
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