649 lines
17 KiB
C
649 lines
17 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SiS 85c496/85c497 chip.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2019,2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/timer.h>
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#include <86box/dma.h>
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#include <86box/nvr.h>
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#include <86box/pic.h>
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#include <86box/port_92.h>
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#include <86box/hdc_ide.h>
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#include <86box/machine.h>
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#include <86box/chipset.h>
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#include <86box/spd.h>
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typedef struct sis_85c496_t
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{
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uint8_t cur_reg, rmsmiblk_count,
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regs[127],
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pci_conf[256];
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pc_timer_t rmsmiblk_timer;
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port_92_t * port_92;
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nvr_t * nvr;
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} sis_85c496_t;
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#ifdef ENABLE_SIS_85C496_LOG
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int sis_85c496_do_log = ENABLE_SIS_85C496_LOG;
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void
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sis_85c496_log(const char *fmt, ...)
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{
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va_list ap;
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if (sis_85c496_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define sis_85c496_log(fmt, ...)
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#endif
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static void
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sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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sis_85c496_log("[%04X:%08X] ISA Write %02X to %04X\n", CS, cpu_state.pc, val, port);
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if (port == 0x22)
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dev->cur_reg = val;
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else if (port == 0x23) switch (dev->cur_reg) {
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case 0x01: /* Built-in 206 Timing Control */
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dev->regs[dev->cur_reg] = val;
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break;
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case 0x70: /* ISA Bus Clock Selection */
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dev->regs[dev->cur_reg] = val & 0xc0;
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break;
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case 0x71: /* ISA Bus Timing Control */
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dev->regs[dev->cur_reg] = val & 0xf6;
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break;
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case 0x72: case 0x76: /* SMOUT */
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case 0x74: /* BIOS Timer */
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dev->regs[dev->cur_reg] = val;
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break;
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case 0x73: /* BIOS Timer */
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dev->regs[dev->cur_reg] = val & 0xfd;
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break;
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case 0x75: /* DMA / Deturbo Control */
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dev->regs[dev->cur_reg] = val & 0xfc;
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dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff);
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break;
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}
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}
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static uint8_t
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sis_85c497_isa_read(uint16_t port, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t ret = 0xff;
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if (port == 0x23)
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ret = dev->regs[dev->cur_reg];
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else if (port == 0x33)
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ret = 0x3c /*random_generate()*/;
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sis_85c496_log("[%04X:%08X] ISA Read %02X from %04X\n", CS, cpu_state.pc, ret, port);
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return ret;
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}
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static void
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sis_85c496_recalcmapping(sis_85c496_t *dev)
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{
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uint32_t base;
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uint32_t i, shflags = 0;
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shadowbios = 0;
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shadowbios_write = 0;
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for (i = 0; i < 8; i++) {
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base = 0xc0000 + (i << 15);
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if (dev->pci_conf[0x44] & (1 << i)) {
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shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02);
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shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01);
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shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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mem_set_mem_state_both(base, 0x8000, shflags);
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} else
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mem_set_mem_state_both(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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}
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static void
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sis_85c496_ide_handler(sis_85c496_t *dev)
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{
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uint8_t ide_cfg[2];
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ide_cfg[0] = dev->pci_conf[0x58];
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ide_cfg[1] = dev->pci_conf[0x59];
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ide_pri_disable();
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ide_sec_disable();
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if (ide_cfg[1] & 0x02) {
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ide_set_base(0, 0x0170);
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ide_set_side(0, 0x0376);
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ide_set_base(1, 0x01f0);
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ide_set_side(1, 0x03f6);
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if (ide_cfg[1] & 0x01) {
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if (!(ide_cfg[0] & 0x40))
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ide_pri_enable();
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if (!(ide_cfg[0] & 0x80))
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ide_sec_enable();
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}
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} else {
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ide_set_base(0, 0x01f0);
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ide_set_side(0, 0x03f6);
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ide_set_base(1, 0x0170);
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ide_set_side(1, 0x0376);
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if (ide_cfg[1] & 0x01) {
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if (!(ide_cfg[0] & 0x40))
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ide_sec_enable();
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if (!(ide_cfg[0] & 0x80))
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ide_pri_enable();
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}
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}
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}
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static void
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sis_85c496_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
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{
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mem_set_mem_state_smram(smm, addr, size, is_smram);
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flushmmucache();
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}
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/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
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static void
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sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t old, valxor;
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uint8_t smm_irq[4] = { 10, 11, 12, 15 };
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old = dev->pci_conf[addr];
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valxor = (dev->pci_conf[addr]) ^ val;
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sis_85c496_log("[%04X:%08X] PCI Write %02X to %02X:%02X\n", CS, cpu_state.pc, val, func, addr);
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switch (addr) {
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/* PCI Configuration Header Registers (00h ~ 3Fh) */
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case 0x04: /* PCI Device Command */
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dev->pci_conf[addr] = val & 0x40;
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break;
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case 0x05: /* PCI Device Command */
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dev->pci_conf[addr] = val & 0x03;
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break;
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case 0x07: /* Device Status */
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dev->pci_conf[addr] &= ~(val & 0xf1);
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break;
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/* 86C496 Specific Registers (40h ~ 7Fh) */
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case 0x40: /* CPU Configuration */
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dev->pci_conf[addr] = val & 0x7f;
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break;
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case 0x41: /* DRAM Configuration */
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dev->pci_conf[addr] = val;
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break;
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case 0x42: /* Cache Configure */
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dev->pci_conf[addr] = val;
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cpu_cache_ext_enabled = (val & 0x01);
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cpu_update_waitstates();
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break;
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case 0x43: /* Cache Configure */
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dev->pci_conf[addr] = val & 0x8f;
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break;
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case 0x44: /* Shadow Configure */
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dev->pci_conf[addr] = val;
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if (valxor & 0xff) {
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sis_85c496_recalcmapping(dev);
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if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x30))
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flushmmucache_nopc();
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else
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flushmmucache();
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}
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break;
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case 0x45: /* Shadow Configure */
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dev->pci_conf[addr] = val & 0x0f;
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if (valxor & 0x03) {
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sis_85c496_recalcmapping(dev);
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flushmmucache();
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}
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break;
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case 0x46: /* Cacheable Control */
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dev->pci_conf[addr] = val;
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break;
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case 0x47: /* 85C496 Address Decoder */
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dev->pci_conf[addr] = val & 0x1f;
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break;
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case 0x48: case 0x49: case 0x4a: case 0x4b: /* DRAM Boundary */
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case 0x4c: case 0x4d: case 0x4e: case 0x4f:
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// dev->pci_conf[addr] = val;
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spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1);
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break;
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case 0x50: case 0x51: /* Exclusive Area 0 Setup */
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dev->pci_conf[addr] = val;
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break;
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case 0x52: case 0x53: /* Exclusive Area 1 Setup */
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dev->pci_conf[addr] = val;
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break;
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case 0x54: /* Exclusive Area 2 Setup */
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dev->pci_conf[addr] = val;
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break;
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case 0x55: /* Exclusive Area 3 Setup */
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dev->pci_conf[addr] = val & 0xf0;
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break;
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case 0x56: /* PCI / Keyboard Configure */
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dev->pci_conf[addr] = val;
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if (valxor & 0x02) {
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port_92_remove(dev->port_92);
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if (val & 0x02)
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port_92_add(dev->port_92);
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}
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break;
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case 0x57: /* Output Pin Configuration */
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dev->pci_conf[addr] = val;
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break;
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case 0x58: /* Build-in IDE Controller / VESA Bus Configuration */
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dev->pci_conf[addr] = val & 0xd7;
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if (valxor & 0xc0)
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sis_85c496_ide_handler(dev);
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break;
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case 0x59: /* Build-in IDE Controller / VESA Bus Configuration */
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dev->pci_conf[addr] = val;
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if (valxor & 0x03)
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sis_85c496_ide_handler(dev);
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break;
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case 0x5a: /* SMRAM Remapping Configuration */
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dev->pci_conf[addr] = val & 0xbe;
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if (valxor & 0x3e) {
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unmask_a20_in_smm = !!(val & 0x20);
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if (smram[0].size != 0x00000000) {
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sis_85c496_smram_map(0, smram[0].host_base, smram[0].size, 0);
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sis_85c496_smram_map(1, smram[0].host_base, smram[0].size, 0);
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memset(&smram[0], 0x00, sizeof(smram_t));
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mem_mapping_disable(&ram_smram_mapping[0]);
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}
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if (val & 0x06) {
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smram[0].size = 0x00010000;
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switch ((val >> 3) & 0x03) {
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case 0x00:
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smram[0].host_base = 0x00060000;
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smram[0].ram_base = 0x000a0000;
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break;
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case 0x01:
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smram[0].host_base = 0x00060000;
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smram[0].ram_base = 0x000b0000;
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break;
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case 0x02:
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smram[0].host_base = 0x000e0000;
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smram[0].ram_base = 0x000a0000;
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break;
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case 0x03:
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smram[0].host_base = 0x000e0000;
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smram[0].ram_base = 0x000b0000;
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break;
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}
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mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, 0x00010000);
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mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
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sis_85c496_smram_map(0, smram[0].host_base, smram[0].size, ((val & 0x06) == 0x06));
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sis_85c496_smram_map(1, smram[0].host_base, smram[0].size, (val & 0x02));
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}
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}
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break;
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case 0x5b: /* Programmable I/O Traps Configure */
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case 0x5c: case 0x5d: /* Programmable I/O Trap 0 Base */
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case 0x5e: case 0x5f: /* Programmable I/O Trap 0 Base */
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case 0x60: case 0x61: /* IDE Controller Channel 0 Configuration */
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case 0x62: case 0x63: /* IDE Controller Channel 1 Configuration */
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case 0x64: case 0x65: /* Exclusive Area 3 Setup */
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case 0x66: /* EDO DRAM Configuration */
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case 0x68: case 0x69: /* Asymmetry DRAM Configuration */
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dev->pci_conf[addr] = val;
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break;
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case 0x67: /* Miscellaneous Control */
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dev->pci_conf[addr] = val & 0xf9;
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if (valxor & 0x60)
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port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
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break;
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/* 86C497 Specific Registers (80h ~ FFh) */
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case 0x80: /* PMU Configuration */
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case 0x85: /* STPCLK# Event Control */
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case 0x86: case 0x87: /* STPCLK# Deassertion IRQ Selection */
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case 0x89: /* Fast Timer Count */
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case 0x8a: /* Generic Timer Count */
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case 0x8b: /* Slow Timer Count */
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case 0x8e: /* Clock Throttling On Timer Count */
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case 0x8f: /* Clock Throttling Off Timer Count */
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case 0x90: /* Clock Throttling On Timer Reload Condition */
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case 0x92: /* Fast Timer Reload Condition */
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case 0x94: /* Generic Timer Reload Condition */
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case 0x96: /* Slow Timer Reload Condition */
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case 0x98: case 0x99: /* Fast Timer Reload IRQ Selection */
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case 0x9a: case 0x9b: /* Generic Timer Reload IRQ Selection */
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case 0x9c: case 0x9d: /* Slow Timer Reload IRQ Selection */
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case 0xa2: /* SMI Request Status Selection */
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case 0xa4: case 0xa5: /* SMI Request IRQ Selection */
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case 0xa6: case 0xa7: /* Clock Throttlign On Timer Reload IRQ Selection */
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case 0xa8: /* GPIO Control */
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case 0xaa: /* GPIO DeBounce Count */
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case 0xd2: /* Exclusive Area 2 Base Address */
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dev->pci_conf[addr] = val;
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break;
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case 0x81: /* PMU CPU Type Configuration */
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dev->pci_conf[addr] = val & 0x9f;
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break;
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case 0x88: /* Timer Control */
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dev->pci_conf[addr] = val & 0x3f;
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break;
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case 0x8d: /* RMSMIBLK Timer Count */
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dev->pci_conf[addr] = val;
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dev->rmsmiblk_count = val;
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timer_stop(&dev->rmsmiblk_timer);
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if (val >= 0x02)
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timer_on_auto(&dev->rmsmiblk_timer, 35.0);
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break;
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case 0x91: /* Clock Throttling On Timer Reload Condition */
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case 0x93: /* Fast Timer Reload Condition */
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case 0x95: /* Generic Timer Reload Condition */
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dev->pci_conf[addr] = val & 0x03;
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break;
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case 0x97: /* Slow Timer Reload Condition */
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dev->pci_conf[addr] = val & 0xc3;
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break;
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case 0x9e: /* Soft-SMI Generation / RMSMIBLK Trigger */
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if (!smi_block && (val & 0x01) && (dev->pci_conf[0x80] & 0x80) && (dev->pci_conf[0xa2] & 0x10)) {
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if (dev->pci_conf[0x80] & 0x10)
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picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]);
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else
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smi_line = 1;
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smi_block = 1;
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dev->pci_conf[0xa0] |= 0x10;
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}
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if (val & 0x02) {
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timer_stop(&dev->rmsmiblk_timer);
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if (dev->rmsmiblk_count >= 0x02)
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timer_on_auto(&dev->rmsmiblk_timer, 35.0);
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}
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break;
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case 0xa0: case 0xa1: /* SMI Request Status */
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dev->pci_conf[addr] &= ~val;
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break;
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case 0xa3: /* SMI Request Status Selection */
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dev->pci_conf[addr] = val & 0x7f;
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break;
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case 0xa9: /* GPIO SMI Request Status */
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dev->pci_conf[addr] = ~(val & 0x03);
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break;
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case 0xc0: /* PCI INTA# -to-IRQ Link */
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case 0xc1: /* PCI INTB# -to-IRQ Link */
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case 0xc2: /* PCI INTC# -to-IRQ Link */
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case 0xc3: /* PCI INTD# -to-IRQ Link */
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dev->pci_conf[addr] = val & 0x8f;
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf);
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else
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pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED);
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break;
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case 0xc6: /* 85C497 Post / INIT Configuration */
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dev->pci_conf[addr] = val & 0x0f;
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break;
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case 0xc8: case 0xc9: case 0xca: case 0xcb: /* Mail Box */
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dev->pci_conf[addr] = val;
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break;
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case 0xd0: /* ISA BIOS Configuration */
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dev->pci_conf[addr] = val & 0xfb;
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break;
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case 0xd1: /* ISA Address Decoder */
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if (dev->pci_conf[0xd0] & 0x01)
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dev->pci_conf[addr] = val;
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break;
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case 0xd3: /* Exclusive Area 2 Base Address */
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dev->pci_conf[addr] = val & 0xf0;
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break;
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case 0xd4: /* Miscellaneous Configuration */
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dev->pci_conf[addr] = val & 0x6e;
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nvr_bank_set(0, !!(val & 0x40), dev->nvr);
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break;
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}
|
|
}
|
|
|
|
|
|
static uint8_t
|
|
sis_85c49x_pci_read(int func, int addr, void *priv)
|
|
{
|
|
sis_85c496_t *dev = (sis_85c496_t *) priv;
|
|
uint8_t ret = dev->pci_conf[addr];
|
|
|
|
switch (addr) {
|
|
case 0x82: /*Port 22h Mirror*/
|
|
ret = dev->cur_reg;
|
|
break;
|
|
case 0x83: /*Port 70h Mirror*/
|
|
ret = inb(0x70);
|
|
break;
|
|
}
|
|
|
|
sis_85c496_log("[%04X:%08X] PCI Read %02X from %02X:%02X\n", CS, cpu_state.pc, ret, func, addr);
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
static void
|
|
sis_85c496_rmsmiblk_count(void *priv)
|
|
{
|
|
sis_85c496_t *dev = (sis_85c496_t *) priv;
|
|
|
|
dev->rmsmiblk_count--;
|
|
|
|
if (dev->rmsmiblk_count == 1) {
|
|
smi_block = 0;
|
|
dev->rmsmiblk_count = 0;
|
|
timer_stop(&dev->rmsmiblk_timer);
|
|
} else
|
|
timer_on_auto(&dev->rmsmiblk_timer, 35.0);
|
|
}
|
|
|
|
|
|
static void
|
|
sis_85c497_isa_reset(sis_85c496_t *dev)
|
|
{
|
|
memset(dev->regs, 0, sizeof(dev->regs));
|
|
|
|
dev->regs[0x01] = 0xc0;
|
|
dev->regs[0x71] = 0x01;
|
|
dev->regs[0x72] = 0xff;
|
|
dev->regs[0x76] = 0xff;
|
|
|
|
dma_set_mask(0x00ffffff);
|
|
|
|
io_removehandler(0x0022, 0x0002,
|
|
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
|
|
io_removehandler(0x0033, 0x0001,
|
|
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
|
|
io_sethandler(0x0022, 0x0002,
|
|
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
|
|
io_sethandler(0x0033, 0x0001,
|
|
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
|
|
}
|
|
|
|
|
|
static void
|
|
sis_85c496_reset(void *priv)
|
|
{
|
|
sis_85c496_t *dev = (sis_85c496_t *) priv;
|
|
int i;
|
|
|
|
sis_85c49x_pci_write(0, 0x44, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x45, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
|
|
|
|
for (i = 0; i < 8; i++)
|
|
sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev);
|
|
|
|
sis_85c49x_pci_write(0, 0x80, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x81, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x9e, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0x8d, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xa0, 0xff, dev);
|
|
sis_85c49x_pci_write(0, 0xa1, 0xff, dev);
|
|
sis_85c49x_pci_write(0, 0xc0, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xc1, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xc2, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xc3, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xc8, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xc9, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xca, 0x00, dev);
|
|
sis_85c49x_pci_write(0, 0xcb, 0x00, dev);
|
|
|
|
sis_85c49x_pci_write(0, 0xd0, 0x79, dev);
|
|
sis_85c49x_pci_write(0, 0xd1, 0xff, dev);
|
|
sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
|
|
sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
|
|
|
|
ide_pri_disable();
|
|
ide_sec_disable();
|
|
|
|
nvr_bank_set(0, 0, dev->nvr);
|
|
|
|
sis_85c497_isa_reset(dev);
|
|
}
|
|
|
|
|
|
static void
|
|
sis_85c496_close(void *p)
|
|
{
|
|
sis_85c496_t *sis_85c496 = (sis_85c496_t *)p;
|
|
|
|
free(sis_85c496);
|
|
}
|
|
|
|
|
|
static void
|
|
*sis_85c496_init(const device_t *info)
|
|
{
|
|
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
|
|
memset(dev, 0x00, sizeof(sis_85c496_t));
|
|
|
|
/* PCI Configuration Header Registers (00h ~ 3Fh) */
|
|
dev->pci_conf[0x00] = 0x39; /* SiS */
|
|
dev->pci_conf[0x01] = 0x10;
|
|
dev->pci_conf[0x02] = 0x96; /* 496/497 */
|
|
dev->pci_conf[0x03] = 0x04;
|
|
dev->pci_conf[0x04] = 0x07;
|
|
dev->pci_conf[0x06] = 0x80;
|
|
dev->pci_conf[0x07] = 0x02;
|
|
dev->pci_conf[0x08] = 0x02; /* Device revision */
|
|
dev->pci_conf[0x09] = 0x00; /* Device class (PCI bridge) */
|
|
dev->pci_conf[0x0b] = 0x06;
|
|
|
|
/* 86C496 Specific Registers (40h ~ 7Fh) */
|
|
|
|
/* 86C497 Specific Registers (80h ~ FFh) */
|
|
dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */
|
|
dev->pci_conf[0xd1] = 0xff;
|
|
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
|
|
|
|
sis_85c497_isa_reset(dev);
|
|
|
|
dev->port_92 = device_add(&port_92_device);
|
|
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
|
|
port_92_set_features(dev->port_92, 0, 0);
|
|
|
|
sis_85c496_recalcmapping(dev);
|
|
|
|
ide_pri_disable();
|
|
ide_sec_disable();
|
|
|
|
if (info->local)
|
|
dev->nvr = device_add(&ls486e_nvr_device);
|
|
else
|
|
dev->nvr = device_add(&at_nvr_device);
|
|
|
|
dma_high_page_init();
|
|
|
|
timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
|
|
|
|
return dev;
|
|
}
|
|
|
|
|
|
const device_t sis_85c496_device =
|
|
{
|
|
"SiS 85c496/85c497",
|
|
DEVICE_PCI,
|
|
0,
|
|
sis_85c496_init,
|
|
sis_85c496_close,
|
|
sis_85c496_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|
|
|
|
|
|
const device_t sis_85c496_ls486e_device =
|
|
{
|
|
"SiS 85c496/85c497 (Lucky Star LS-486E)",
|
|
DEVICE_PCI,
|
|
1,
|
|
sis_85c496_init,
|
|
sis_85c496_close,
|
|
sis_85c496_reset,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|