311 lines
9.0 KiB
C
311 lines
9.0 KiB
C
static int opMOV_r_CRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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cpu_state.regs[cpu_rm].l = cr0;
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if (is486 || isibm486)
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cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
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else {
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if (is386)
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cpu_state.regs[cpu_rm].l |=0x7fffffe0;
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else
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cpu_state.regs[cpu_rm].l |=0x7ffffff0;
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}
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break;
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case 2:
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cpu_state.regs[cpu_rm].l = cr2;
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break;
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case 3:
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cpu_state.regs[cpu_rm].l = cr3;
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break;
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case 4:
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if (cpu_has_feature(CPU_FEATURE_CR4))
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{
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cpu_state.regs[cpu_rm].l = cr4;
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break;
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}
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_CRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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cpu_state.regs[cpu_rm].l = cr0;
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if (is486 || isibm486)
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cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
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else {
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if (is386)
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cpu_state.regs[cpu_rm].l |=0x7fffffe0;
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else
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cpu_state.regs[cpu_rm].l |=0x7ffffff0;
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}
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break;
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case 2:
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cpu_state.regs[cpu_rm].l = cr2;
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break;
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case 3:
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cpu_state.regs[cpu_rm].l = cr3;
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break;
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case 4:
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if (cpu_has_feature(CPU_FEATURE_CR4))
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{
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cpu_state.regs[cpu_rm].l = cr4;
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break;
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}
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_r_DRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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cpu_state.regs[cpu_rm].l = dr[cpu_reg];
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_DRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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cpu_state.regs[cpu_rm].l = dr[cpu_reg];
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_CRx_r_a16(uint32_t fetchdat)
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{
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uint32_t old_cr0 = cr0;
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL,0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
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flushmmucache();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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cr0 = cpu_state.regs[cpu_rm].l;
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if (cpu_16bitbus)
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cr0 |= 0x10;
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if (!(cr0 & 0x80000000))
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mmu_perm=4;
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if (hascache && !(cr0 & (1 << 30)))
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cpu_cache_int_enabled = 1;
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else
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cpu_cache_int_enabled = 0;
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if (hascache && ((cr0 ^ old_cr0) & (1 << 30)))
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cpu_update_waitstates();
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if (cr0 & 1)
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cpu_cur_status |= CPU_STATUS_PMODE;
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else
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cpu_cur_status &= ~CPU_STATUS_PMODE;
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break;
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case 2:
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cr2 = cpu_state.regs[cpu_rm].l;
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break;
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case 3:
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cr3 = cpu_state.regs[cpu_rm].l;
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flushmmucache();
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break;
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case 4:
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if (cpu_has_feature(CPU_FEATURE_CR4))
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{
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if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE)
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flushmmucache();
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cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
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break;
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}
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(10);
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PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_CRx_r_a32(uint32_t fetchdat)
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{
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uint32_t old_cr0 = cr0;
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL,0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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switch (cpu_reg)
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{
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case 0:
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if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
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flushmmucache();
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/* Make sure CPL = 0 when switching from real mode to protected mode. */
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if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
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cpu_state.seg_cs.access &= 0x9f;
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cr0 = cpu_state.regs[cpu_rm].l;
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if (cpu_16bitbus)
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cr0 |= 0x10;
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if (!(cr0 & 0x80000000))
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mmu_perm=4;
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if (hascache && !(cr0 & (1 << 30)))
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cpu_cache_int_enabled = 1;
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else
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cpu_cache_int_enabled = 0;
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if (hascache && ((cr0 ^ old_cr0) & (1 << 30)))
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cpu_update_waitstates();
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if (cr0 & 1)
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cpu_cur_status |= CPU_STATUS_PMODE;
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else
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cpu_cur_status &= ~CPU_STATUS_PMODE;
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break;
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case 2:
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cr2 = cpu_state.regs[cpu_rm].l;
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break;
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case 3:
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cr3 = cpu_state.regs[cpu_rm].l;
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flushmmucache();
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break;
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case 4:
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if (cpu_has_feature(CPU_FEATURE_CR4))
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{
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if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE)
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flushmmucache();
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cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
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break;
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}
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default:
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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break;
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}
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CLOCK_CYCLES(10);
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PREFETCH_RUN(10, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_DRx_r_a16(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_DRx_r_a32(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_r_TRx_a16(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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cpu_state.regs[cpu_rm].l = 0;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_r_TRx_a32(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_32(fetchdat);
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cpu_state.regs[cpu_rm].l = 0;
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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static int opMOV_TRx_r_a16(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 0);
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return 0;
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}
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static int opMOV_TRx_r_a32(uint32_t fetchdat)
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{
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if ((CPL || (cpu_state.eflags&VM_FLAG)) && (cr0&1))
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{
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x86gpf(NULL, 0);
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return 1;
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}
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fetch_ea_16(fetchdat);
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CLOCK_CYCLES(6);
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PREFETCH_RUN(6, 2, rmdat, 0,0,0,0, 1);
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return 0;
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}
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