a505894a10
- 86Box's own headers go to /86box - munt's public interface goes to /mt32emu - all slirp headers go to /slirp (might want to consider using only its public inteface) - single file headers from other projects go in include root
343 lines
7.2 KiB
C
343 lines
7.2 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SiS 85c496/85c497 chip.
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2019 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/timer.h>
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#include <86box/port_92.h>
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#include <86box/hdc_ide.h>
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#include <86box/machine.h>
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#include <86box/chipset.h>
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typedef struct sis_85c496_t
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{
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uint8_t cur_reg,
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regs[127],
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pci_conf[256];
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port_92_t * port_92;
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} sis_85c496_t;
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static void
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sis_85c497_write(uint16_t port, uint8_t val, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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if (index) {
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if ((val != 0x01) || ((val >= 0x70) && (val <= 0x76)))
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dev->cur_reg = val;
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} else {
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if (((dev->cur_reg < 0x70) && (dev->cur_reg != 0x01)) || (dev->cur_reg > 0x76))
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return;
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dev->regs[dev->cur_reg] = val;
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dev->cur_reg = 0;
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}
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}
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static uint8_t
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sis_85c497_read(uint16_t port, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t ret = 0xff;
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if (index)
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ret = dev->cur_reg;
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else {
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if ((dev->cur_reg != 0x01) || ((dev->cur_reg >= 0x70) && (dev->cur_reg <= 0x76))) {
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ret = dev->regs[dev->cur_reg];
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dev->cur_reg = 0;
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}
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}
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return ret;
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}
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static void
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sis_85c496_recalcmapping(sis_85c496_t *dev)
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{
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uint32_t base;
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uint32_t i, shflags = 0;
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shadowbios = 0;
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shadowbios_write = 0;
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for (i = 0; i < 8; i++) {
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base = 0xc0000 + (i << 15);
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if (dev->pci_conf[0x44] & (1 << i)) {
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shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02);
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shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01);
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shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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mem_set_mem_state(base, 0x8000, shflags);
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} else
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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flushmmucache();
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}
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/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
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static void
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sis_85c496_write(int func, int addr, uint8_t val, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t old = dev->pci_conf[addr];
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uint8_t valxor;
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if ((addr >= 4 && addr < 8) || addr >= 0x40)
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dev->pci_conf[addr] = val;
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valxor = old ^ val;
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switch (addr) {
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case 0x42: /*Cache configure*/
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cpu_cache_ext_enabled = (val & 0x01);
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cpu_update_waitstates();
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break;
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case 0x44: /*Shadow configure*/
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if (valxor & 0xff)
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sis_85c496_recalcmapping(dev);
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break;
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case 0x45: /*Shadow configure*/
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if (valxor & 0x03)
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sis_85c496_recalcmapping(dev);
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break;
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case 0x56:
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if (valxor & 0x02) {
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port_92_remove(dev->port_92);
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if (val & 0x02)
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port_92_add(dev->port_92);
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}
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break;
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case 0x59:
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if (valxor & 0x02) {
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if (val & 0x02) {
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ide_set_base(0, 0x0170);
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ide_set_side(0, 0x0376);
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ide_set_base(1, 0x01f0);
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ide_set_side(1, 0x03f6);
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} else {
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ide_set_base(0, 0x01f0);
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ide_set_side(0, 0x03f6);
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ide_set_base(1, 0x0170);
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ide_set_side(1, 0x0376);
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}
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}
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break;
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case 0x58:
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if (valxor & 0x80) {
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if (dev->pci_conf[0x59] & 0x02) {
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ide_sec_disable();
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if (val & 0x80)
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ide_sec_enable();
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} else {
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ide_pri_disable();
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if (val & 0x80)
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ide_pri_enable();
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}
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}
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if (valxor & 0x40) {
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if (dev->pci_conf[0x59] & 0x02) {
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ide_pri_disable();
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if (val & 0x40)
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ide_pri_enable();
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} else {
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ide_sec_disable();
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if (val & 0x40)
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ide_sec_enable();
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}
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}
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break;
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case 0x5a:
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if (valxor & 0x04) {
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if (val & 0x04)
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mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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break;
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case 0x67:
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if (valxor & 0x60)
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port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
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break;
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case 0x82:
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sis_85c497_write(0x22, val, priv);
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break;
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case 0xc0:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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break;
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case 0xc1:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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break;
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case 0xc2:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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break;
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case 0xc3:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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break;
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}
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}
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static uint8_t
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sis_85c496_read(int func, int addr, void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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uint8_t ret = dev->pci_conf[addr];
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switch (addr) {
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case 0x82: /*Port 22h Mirror*/
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ret = inb(0x22);
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break;
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case 0x70: /*Port 70h Mirror*/
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ret = inb(0x70);
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break;
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}
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return ret;
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}
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static void
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sis_85c497_reset(sis_85c496_t *dev)
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{
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memset(dev->regs, 0, sizeof(dev->regs));
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dev->regs[0x01] = 0xc0;
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dev->regs[0x71] = 0x01;
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dev->regs[0x72] = 0xff;
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io_removehandler(0x0022, 0x0002,
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sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
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io_sethandler(0x0022, 0x0002,
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sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
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}
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static void
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sis_85c496_reset(void *priv)
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{
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sis_85c496_t *dev = (sis_85c496_t *) priv;
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sis_85c497_reset(dev);
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}
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static void
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sis_85c496_close(void *p)
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{
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sis_85c496_t *sis_85c496 = (sis_85c496_t *)p;
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free(sis_85c496);
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}
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static void
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*sis_85c496_init(const device_t *info)
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{
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sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
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memset(dev, 0, sizeof(sis_85c496_t));
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dev->pci_conf[0x00] = 0x39; /*SiS*/
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x96; /*496/497*/
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dev->pci_conf[0x03] = 0x04;
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dev->pci_conf[0x04] = 7;
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dev->pci_conf[0x05] = 0;
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dev->pci_conf[0x06] = 0x80;
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dev->pci_conf[0x07] = 0x02;
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dev->pci_conf[0x08] = 2; /*Device revision*/
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dev->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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dev->pci_conf[0x0a] = 0x00;
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dev->pci_conf[0x0b] = 0x06;
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dev->pci_conf[0x0e] = 0x00; /*Single function device*/
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dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */
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dev->pci_conf[0xd1] = 0xff;
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pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c496_read, sis_85c496_write, dev);
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sis_85c497_reset(dev);
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dev->port_92 = device_add(&port_92_device);
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port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
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port_92_set_features(dev->port_92, 0, 0);
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sis_85c496_recalcmapping(dev);
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return dev;
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}
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const device_t sis_85c496_device =
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{
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"SiS 85c496/85c497",
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DEVICE_PCI,
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0,
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sis_85c496_init,
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sis_85c496_close,
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sis_85c496_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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