632 lines
18 KiB
C
632 lines
18 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SMC FDC37C67X Super I/O Chip.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2016-2018 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/pic.h>
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#include <86box/pci.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include "cpu.h"
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#include <86box/sio.h>
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#include <86box/plat_unused.h>
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#define AB_RST 0x80
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typedef struct fdc37c67x_t {
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uint8_t chip_id;
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uint8_t is_apm;
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uint8_t tries;
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uint8_t gpio_regs[2];
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uint8_t auxio_reg;
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uint8_t regs[48];
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uint8_t ld_regs[11][256];
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uint16_t gpio_base; /* Set to EA */
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uint16_t auxio_base;
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uint16_t sio_base;
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int locked;
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int cur_reg;
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fdc_t *fdc;
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serial_t *uart[2];
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} fdc37c67x_t;
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static void fdc37c67x_write(uint16_t port, uint8_t val, void *priv);
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static uint8_t fdc37c67x_read(uint16_t port, void *priv);
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static uint16_t
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make_port(fdc37c67x_t *dev, uint8_t ld)
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{
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uint16_t r0 = dev->ld_regs[ld][0x60];
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uint16_t r1 = dev->ld_regs[ld][0x61];
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uint16_t p = (r0 << 8) + r1;
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return p;
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}
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static uint8_t
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fdc37c67x_auxio_read(UNUSED(uint16_t port), void *priv)
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{
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const fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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return dev->auxio_reg;
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}
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static void
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fdc37c67x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv)
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{
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fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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dev->auxio_reg = val;
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}
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static uint8_t
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fdc37c67x_gpio_read(uint16_t port, void *priv)
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{
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const fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->gpio_regs[port & 1];
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return ret;
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}
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static void
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fdc37c67x_gpio_write(uint16_t port, uint8_t val, void *priv)
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{
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fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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if (!(port & 1))
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dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
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}
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static void
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fdc37c67x_fdc_handler(fdc37c67x_t *dev)
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{
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uint16_t ld_port = 0;
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uint8_t global_enable = !!(dev->regs[0x22] & (1 << 0));
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uint8_t local_enable = !!dev->ld_regs[0][0x30];
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fdc_remove(dev->fdc);
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if (global_enable && local_enable) {
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ld_port = make_port(dev, 0) & 0xFFF8;
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
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fdc_set_base(dev->fdc, ld_port);
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}
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}
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static void
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fdc37c67x_lpt_handler(fdc37c67x_t *dev)
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{
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uint16_t ld_port = 0;
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uint8_t global_enable = !!(dev->regs[0x22] & (1 << 3));
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uint8_t local_enable = !!dev->ld_regs[3][0x30];
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uint8_t lpt_irq = dev->ld_regs[3][0x70];
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if (lpt_irq > 15)
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lpt_irq = 0xff;
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lpt1_remove();
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if (global_enable && local_enable) {
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ld_port = make_port(dev, 3) & 0xFFFC;
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
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lpt1_setup(ld_port);
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}
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lpt1_irq(lpt_irq);
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}
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static void
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fdc37c67x_serial_handler(fdc37c67x_t *dev, int uart)
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{
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uint16_t ld_port = 0;
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uint8_t uart_no = 4 + uart;
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uint8_t global_enable = !!(dev->regs[0x22] & (1 << uart_no));
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uint8_t local_enable = !!dev->ld_regs[uart_no][0x30];
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serial_remove(dev->uart[uart]);
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if (global_enable && local_enable) {
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ld_port = make_port(dev, uart_no) & 0xFFF8;
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
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serial_setup(dev->uart[uart], ld_port, dev->ld_regs[uart_no][0x70]);
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}
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}
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static void
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fdc37c67x_auxio_handler(fdc37c67x_t *dev)
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{
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uint16_t ld_port = 0;
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uint8_t local_enable = !!dev->ld_regs[8][0x30];
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io_removehandler(dev->auxio_base, 0x0001,
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fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
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if (local_enable) {
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dev->auxio_base = ld_port = make_port(dev, 8);
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if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
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io_sethandler(dev->auxio_base, 0x0001,
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fdc37c67x_auxio_read, NULL, NULL, fdc37c67x_auxio_write, NULL, NULL, dev);
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}
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}
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static void
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fdc37c67x_sio_handler(UNUSED(fdc37c67x_t *dev))
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{
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#if 0
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if (dev->sio_base) {
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io_removehandler(dev->sio_base, 0x0002,
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fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
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}
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dev->sio_base = (((uint16_t) dev->regs[0x27]) << 8) | dev->regs[0x26];
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if (dev->sio_base) {
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io_sethandler(dev->sio_base, 0x0002,
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fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
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}
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#endif
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}
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static void
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fdc37c67x_gpio_handler(fdc37c67x_t *dev)
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{
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uint16_t ld_port = 0;
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uint8_t local_enable;
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local_enable = !!(dev->regs[0x03] & 0x80);
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io_removehandler(dev->gpio_base, 0x0002,
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fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
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if (local_enable) {
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switch (dev->regs[0x03] & 0x03) {
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case 0:
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ld_port = 0xe0;
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break;
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case 1:
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ld_port = 0xe2;
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break;
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case 2:
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ld_port = 0xe4;
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break;
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case 3:
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ld_port = 0xea; /* Default */
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break;
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default:
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break;
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}
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dev->gpio_base = ld_port;
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if (ld_port > 0x0000)
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io_sethandler(dev->gpio_base, 0x0002,
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fdc37c67x_gpio_read, NULL, NULL, fdc37c67x_gpio_write, NULL, NULL, dev);
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}
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}
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static void
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fdc37c67x_smi_handler(fdc37c67x_t *dev)
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{
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/* TODO: 8042 P1.2 SMI#. */
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pic_reset_smi_irq_mask();
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pic_set_smi_irq_mask(dev->ld_regs[3][0x70], dev->ld_regs[8][0xb4] & 0x02);
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pic_set_smi_irq_mask(dev->ld_regs[5][0x70], dev->ld_regs[8][0xb4] & 0x04);
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pic_set_smi_irq_mask(dev->ld_regs[4][0x70], dev->ld_regs[8][0xb4] & 0x08);
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pic_set_smi_irq_mask(dev->ld_regs[0][0x70], dev->ld_regs[8][0xb4] & 0x10);
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pic_set_smi_irq_mask(12, dev->ld_regs[8][0xb5] & 0x01);
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pic_set_smi_irq_mask(1, dev->ld_regs[8][0xb5] & 0x02);
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pic_set_smi_irq_mask(10, dev->ld_regs[8][0xb5] & 0x80);
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}
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static void
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fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
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{
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fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t valxor = 0x00;
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uint8_t keep = 0x00;
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if (index) {
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if ((val == 0x55) && !dev->locked) {
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if (dev->tries) {
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dev->locked = 1;
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fdc_3f1_enable(dev->fdc, 0);
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dev->tries = 0;
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} else
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dev->tries++;
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} else {
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if (dev->locked) {
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if (val == 0xaa) {
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dev->locked = 0;
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fdc_3f1_enable(dev->fdc, 1);
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return;
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}
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dev->cur_reg = val;
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} else {
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if (dev->tries)
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dev->tries = 0;
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}
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}
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return;
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} else {
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if (dev->locked) {
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if (dev->cur_reg < 48) {
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valxor = val ^ dev->regs[dev->cur_reg];
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if ((val == 0x20) || (val == 0x21))
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return;
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dev->regs[dev->cur_reg] = val;
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} else {
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valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg];
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if (((dev->cur_reg & 0xF0) == 0x70) && (dev->regs[7] < 4))
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return;
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/* Block writes to some logical devices. */
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if (dev->regs[7] > 0x0a)
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return;
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else
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switch (dev->regs[7]) {
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case 0x01:
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case 0x02:
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case 0x07:
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return;
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default:
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break;
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}
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dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
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}
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} else
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return;
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}
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if (dev->cur_reg < 48) {
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switch (dev->cur_reg) {
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case 0x03:
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if (valxor & 0x83)
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fdc37c67x_gpio_handler(dev);
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dev->regs[0x03] &= 0x83;
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break;
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case 0x22:
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if (valxor & 0x01)
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fdc37c67x_fdc_handler(dev);
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if (valxor & 0x08)
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fdc37c67x_lpt_handler(dev);
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if (valxor & 0x10)
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fdc37c67x_serial_handler(dev, 0);
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if (valxor & 0x20)
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fdc37c67x_serial_handler(dev, 1);
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break;
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case 0x26:
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case 0x27:
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fdc37c67x_sio_handler(dev);
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break;
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default:
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break;
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}
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return;
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}
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switch (dev->regs[7]) {
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case 0:
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/* FDD */
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switch (dev->cur_reg) {
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case 0x30:
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case 0x60:
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case 0x61:
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if ((dev->cur_reg == 0x30) && (val & 0x01))
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dev->regs[0x22] |= 0x01;
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if (valxor)
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fdc37c67x_fdc_handler(dev);
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break;
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case 0xF0:
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if (valxor & 0x01)
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fdc_update_enh_mode(dev->fdc, val & 0x01);
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if (valxor & 0x10)
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fdc_set_swap(dev->fdc, (val & 0x10) >> 4);
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break;
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case 0xF1:
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if (valxor & 0xC)
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fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2);
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break;
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case 0xF2:
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if (valxor & 0xC0)
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fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
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if (valxor & 0x30)
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fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4);
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if (valxor & 0x0C)
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fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2);
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if (valxor & 0x03)
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fdc_update_rwc(dev->fdc, 0, (val & 0x03));
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break;
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case 0xF4:
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if (valxor & 0x18)
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fdc_update_drvrate(dev->fdc, 0, (val & 0x18) >> 3);
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break;
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case 0xF5:
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if (valxor & 0x18)
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fdc_update_drvrate(dev->fdc, 1, (val & 0x18) >> 3);
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break;
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case 0xF6:
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if (valxor & 0x18)
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fdc_update_drvrate(dev->fdc, 2, (val & 0x18) >> 3);
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break;
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case 0xF7:
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if (valxor & 0x18)
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fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
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break;
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default:
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break;
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}
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break;
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case 3:
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/* Parallel port */
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switch (dev->cur_reg) {
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if ((dev->cur_reg == 0x30) && (val & 0x01))
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dev->regs[0x22] |= 0x08;
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if (valxor)
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fdc37c67x_lpt_handler(dev);
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if (dev->cur_reg == 0x70)
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fdc37c67x_smi_handler(dev);
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break;
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default:
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break;
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}
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break;
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case 4:
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/* Serial port 1 */
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switch (dev->cur_reg) {
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if ((dev->cur_reg == 0x30) && (val & 0x01))
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dev->regs[0x22] |= 0x10;
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if (valxor)
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fdc37c67x_serial_handler(dev, 0);
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if (dev->cur_reg == 0x70)
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fdc37c67x_smi_handler(dev);
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break;
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default:
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break;
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}
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break;
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case 5:
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/* Serial port 2 */
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switch (dev->cur_reg) {
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if ((dev->cur_reg == 0x30) && (val & 0x01))
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dev->regs[0x22] |= 0x20;
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if (valxor)
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fdc37c67x_serial_handler(dev, 1);
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if (dev->cur_reg == 0x70)
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fdc37c67x_smi_handler(dev);
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break;
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default:
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break;
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}
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break;
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case 8:
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/* Auxiliary I/O */
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switch (dev->cur_reg) {
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case 0x30:
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor)
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fdc37c67x_auxio_handler(dev);
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break;
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case 0xb4:
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case 0xb5:
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fdc37c67x_smi_handler(dev);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static uint8_t
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fdc37c67x_read(uint16_t port, void *priv)
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{
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fdc37c67x_t *dev = (fdc37c67x_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t ret = 0xff;
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uint16_t smi_stat = pic_get_smi_irq_status();
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int f_irq = dev->ld_regs[0][0x70];
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int p_irq = dev->ld_regs[3][0x70];
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int s1_irq = dev->ld_regs[4][0x70];
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int s2_irq = dev->ld_regs[5][0x70];
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if (dev->locked) {
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if (index)
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ret = dev->cur_reg;
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else {
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if (dev->cur_reg < 0x30) {
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if (dev->cur_reg == 0x20)
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ret = dev->chip_id;
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else
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ret = dev->regs[dev->cur_reg];
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} else {
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if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
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ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
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} else
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ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
|
|
|
|
/* TODO: 8042 P1.2 SMI#. */
|
|
if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb6)) {
|
|
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0xe1;
|
|
ret |= ((!!(smi_stat & (1 << p_irq))) << 1);
|
|
ret |= ((!!(smi_stat & (1 << s2_irq))) << 2);
|
|
ret |= ((!!(smi_stat & (1 << s1_irq))) << 3);
|
|
ret |= ((!!(smi_stat & (1 << f_irq))) << 4);
|
|
} else if ((dev->regs[7] == 8) && (dev->cur_reg == 0xb7)) {
|
|
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0xec;
|
|
ret |= ((!!(smi_stat & (1 << 12))) << 0);
|
|
ret |= ((!!(smi_stat & (1 << 1))) << 1);
|
|
ret |= ((!!(smi_stat & (1 << 10))) << 4);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
fdc37c67x_reset(fdc37c67x_t *dev)
|
|
{
|
|
memset(dev->regs, 0, 48);
|
|
|
|
dev->regs[0x03] = 0x03;
|
|
dev->regs[0x20] = dev->chip_id;
|
|
dev->regs[0x22] = 0x39;
|
|
dev->regs[0x24] = 0x04;
|
|
dev->regs[0x26] = 0xf0;
|
|
dev->regs[0x27] = 0x03;
|
|
|
|
for (uint8_t i = 0; i < 11; i++)
|
|
memset(dev->ld_regs[i], 0, 256);
|
|
|
|
/* Logical device 0: FDD */
|
|
dev->ld_regs[0][0x30] = 1;
|
|
dev->ld_regs[0][0x60] = 3;
|
|
dev->ld_regs[0][0x61] = 0xf0;
|
|
dev->ld_regs[0][0x70] = 6;
|
|
dev->ld_regs[0][0x74] = 2;
|
|
dev->ld_regs[0][0xf0] = 0x0e;
|
|
dev->ld_regs[0][0xf2] = 0xff;
|
|
|
|
/* Logical device 3: Parallel Port */
|
|
dev->ld_regs[3][0x30] = 1;
|
|
dev->ld_regs[3][0x60] = 3;
|
|
dev->ld_regs[3][0x61] = 0x78;
|
|
dev->ld_regs[3][0x70] = 7;
|
|
dev->ld_regs[3][0x74] = 4;
|
|
dev->ld_regs[3][0xf0] = 0x3c;
|
|
|
|
/* Logical device 4: Serial Port 1 */
|
|
dev->ld_regs[4][0x30] = 1;
|
|
dev->ld_regs[4][0x60] = 3;
|
|
dev->ld_regs[4][0x61] = 0xf8;
|
|
dev->ld_regs[4][0x70] = 4;
|
|
dev->ld_regs[4][0xf0] = 3;
|
|
serial_setup(dev->uart[0], COM1_ADDR, dev->ld_regs[4][0x70]);
|
|
|
|
/* Logical device 5: Serial Port 2 */
|
|
dev->ld_regs[5][0x30] = 1;
|
|
dev->ld_regs[5][0x60] = 2;
|
|
dev->ld_regs[5][0x61] = 0xf8;
|
|
dev->ld_regs[5][0x70] = 3;
|
|
dev->ld_regs[5][0x74] = 4;
|
|
dev->ld_regs[5][0xf1] = 2;
|
|
dev->ld_regs[5][0xf2] = 3;
|
|
serial_setup(dev->uart[1], COM2_ADDR, dev->ld_regs[5][0x70]);
|
|
|
|
/* Logical device 7: Keyboard */
|
|
dev->ld_regs[7][0x30] = 1;
|
|
dev->ld_regs[7][0x61] = 0x60;
|
|
dev->ld_regs[7][0x70] = 1;
|
|
dev->ld_regs[7][0x72] = 12;
|
|
|
|
/* Logical device 8: Auxiliary I/O */
|
|
dev->ld_regs[8][0xc0] = 6;
|
|
dev->ld_regs[8][0xc1] = 3;
|
|
|
|
fdc37c67x_gpio_handler(dev);
|
|
fdc37c67x_lpt_handler(dev);
|
|
fdc37c67x_serial_handler(dev, 0);
|
|
fdc37c67x_serial_handler(dev, 1);
|
|
fdc37c67x_auxio_handler(dev);
|
|
fdc37c67x_sio_handler(dev);
|
|
|
|
fdc_reset(dev->fdc);
|
|
fdc37c67x_fdc_handler(dev);
|
|
|
|
dev->locked = 0;
|
|
}
|
|
|
|
static void
|
|
fdc37c67x_close(void *priv)
|
|
{
|
|
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
fdc37c67x_init(const device_t *info)
|
|
{
|
|
fdc37c67x_t *dev = (fdc37c67x_t *) calloc(1, sizeof(fdc37c67x_t));
|
|
|
|
dev->fdc = device_add(&fdc_at_smc_device);
|
|
|
|
dev->uart[0] = device_add_inst(&ns16550_device, 1);
|
|
dev->uart[1] = device_add_inst(&ns16550_device, 2);
|
|
|
|
dev->chip_id = info->local & 0xff;
|
|
|
|
dev->gpio_regs[0] = 0xff;
|
|
#if 0
|
|
dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
|
|
#endif
|
|
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
|
|
|
|
fdc37c67x_reset(dev);
|
|
|
|
io_sethandler(FDC_SECONDARY_ADDR, 0x0002,
|
|
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
|
|
io_sethandler(FDC_PRIMARY_ADDR, 0x0002,
|
|
fdc37c67x_read, NULL, NULL, fdc37c67x_write, NULL, NULL, dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t fdc37c67x_device = {
|
|
.name = "SMC FDC37C67X Super I/O",
|
|
.internal_name = "fdc37c67x",
|
|
.flags = 0,
|
|
.local = 0x40,
|
|
.init = fdc37c67x_init,
|
|
.close = fdc37c67x_close,
|
|
.reset = NULL,
|
|
.available = NULL,
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|