5318bc08d8
Merged floppy.c and fdd.c and renamed floppy_*.c (the floppy image format handlers) to fdd_*.c; Reading the AT or PS/2 keyboard controller status no longer clears the transmit timeout bit, fixes error 8601 (mouse error) on the IBM PS/2 Model 80; MMU translate and DMA physical reads and writes now go through _mem_exec instead of directly to ram[], should fix the last remaining problems with remapped mappings; Implemented the Sound gain dialog; Added the resource for the "New floppy image" dialog and the needed functions for the functionality of exporting the currently mounted floppy image as 86F, both of which should be finished in the next commit; Applied the CD-ROM fixes from the PCem commit; Added the "Keep ratio" option for full screen stretch.
746 lines
18 KiB
C
746 lines
18 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of Chips&Technology's SCAT (82C235) chipset.
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*
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* Re-worked version based on the 82C235 datasheet and errata.
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*
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* Version: @(#)m_at_scat.c 1.0.8 2018/01/16
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*
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* Authors: Original by GreatPsycho for PCem.
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* Fred N. van Kempen, <decwiz@yahoo.com>
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*
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* Copyright 2017,2018 Fred N. van Kempen.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../device.h"
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#include "../cpu/cpu.h"
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#include "../cpu/x86.h"
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#include "../floppy/fdd.h"
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#include "../floppy/fdc.h"
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#include "../io.h"
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#include "../mem.h"
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#include "machine.h"
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#define SCAT_DEBUG 1
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#define SCAT_DMA_WS_CTL 0x01
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#define SCAT_VERSION 0x40
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#define SCAT_CLOCK_CTL 0x41
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#define SCAT_PERIPH_CTL 0x44
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#define SCAT_MISC_STATUS 0x45
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#define SCAT_POWER_MGMT 0x46
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#define SCAT_ROM_ENABLE 0x48
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#define SCAT_RAM_WR_PROTECT 0x49
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#define SCAT_SHADOW_RAM_EN_1 0x4a
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#define SCAT_SHADOW_RAM_EN_2 0x4b
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#define SCAT_SHADOW_RAM_EN_3 0x4c
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#define SCAT_DRAM_CONFIG 0x4d
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#define SCAT_EXT_BOUNDARY 0x4e
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#define SCAT_EMS_CTL 0x4f
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#define SCAT_SYS_CTL 0x7f /* port 92 */
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typedef struct {
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uint8_t regs_2x8;
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uint8_t regs_2x9;
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} ems_t;
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static uint8_t scat_regs[128];
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static int scat_index;
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static uint32_t scat_xms_bound;
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static uint8_t scat_ems_reg = 0;
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static ems_t scat_ems[32]; /* EMS page regs */
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static mem_mapping_t scat_mapping[32]; /* EMS pages */
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static mem_mapping_t scat_top_mapping[24]; /* top 384K mapping */
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static mem_mapping_t scat_A000_mapping; /* A000-C000 mapping */
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static mem_mapping_t scat_shadowram_mapping[6]; /* BIOS shadowing */
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static mem_mapping_t scat_high_mapping[16]; /* >1M mapping */
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static void
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shadow_state_update(void)
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{
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int i, val;
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/* TODO - ROMCS enable features should be implemented later. */
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for (i=0; i<24; i++) {
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val = ((scat_regs[SCAT_SHADOW_RAM_EN_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
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if (i < 8) {
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val |= ((scat_regs[SCAT_SHADOW_RAM_EN_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
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} else {
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if ((scat_regs[SCAT_RAM_WR_PROTECT] >> ((i - 8) >> 1)) & 1)
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val |= MEM_WRITE_DISABLED;
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else
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val |= ((scat_regs[SCAT_SHADOW_RAM_EN_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
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}
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mem_set_mem_state((i + 40) << 14, 0x4000, val);
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}
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flushmmucache();
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}
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static void
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set_xms_bound(uint8_t val)
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{
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uint32_t max_xms, max_mem;
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int i;
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max_mem = (mem_size << 10);
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max_xms = (mem_size >= 16384) ? 0xFC0000 : max_mem;
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pclog("SCAT: set_xms_bound(%02x): max_mem=%d, max_xms=%d\n",
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val, max_mem, max_xms);
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switch (val & 0x0f) {
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case 1:
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scat_xms_bound = 0x100000;
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break;
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case 2:
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scat_xms_bound = 0x140000;
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break;
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case 3:
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scat_xms_bound = 0x180000;
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break;
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case 4:
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scat_xms_bound = 0x200000;
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break;
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case 5:
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scat_xms_bound = 0x300000;
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break;
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case 6:
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scat_xms_bound = 0x400000;
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break;
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case 7:
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scat_xms_bound = 0x600000;
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break;
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case 8:
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scat_xms_bound = 0x800000;
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break;
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case 9:
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scat_xms_bound = 0xA00000;
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break;
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case 10:
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scat_xms_bound = 0xC00000;
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break;
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case 11:
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scat_xms_bound = 0xE00000;
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break;
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default:
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scat_xms_bound = max_xms;
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break;
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}
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if ((val & 0x40) == 0 && (scat_regs[SCAT_DRAM_CONFIG] & 0x0f) == 3) {
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if (val != 1) {
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if (mem_size > 1024)
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mem_mapping_disable(&ram_high_mapping);
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for (i=0; i<6; i++)
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mem_mapping_enable(&scat_shadowram_mapping[i]);
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if ((val & 0x0f) == 0)
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scat_xms_bound = 0x160000;
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} else {
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for (i=0; i<6; i++)
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mem_mapping_disable(&scat_shadowram_mapping[i]);
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if (mem_size > 1024)
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mem_mapping_enable(&ram_high_mapping);
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}
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pclog("SCAT: set XMS bound(%02X) = %06X (%dK for EMS)\n",
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val, scat_xms_bound, (0x160000-scat_xms_bound)>>10);
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if (scat_xms_bound > 0x100000)
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mem_set_mem_state(0x100000,
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scat_xms_bound - 0x100000,
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MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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if (scat_xms_bound < 0x160000)
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mem_set_mem_state(scat_xms_bound,
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0x160000 - scat_xms_bound,
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MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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} else {
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for (i=0; i<6; i++)
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mem_mapping_disable(&scat_shadowram_mapping[i]);
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if (mem_size > 1024)
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mem_mapping_enable(&ram_high_mapping);
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if (scat_xms_bound > max_xms)
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scat_xms_bound = max_xms;
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pclog("SCAT: set XMS bound(%02X) = %06X (%dK for EMS)\n",
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val, scat_xms_bound, (max_mem-scat_xms_bound)>>10);
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if (scat_xms_bound > 0x100000)
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mem_set_mem_state(0x100000,
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scat_xms_bound-0x100000,
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MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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if (scat_xms_bound < max_mem)
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mem_set_mem_state(scat_xms_bound,
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(mem_size<<10)-scat_xms_bound,
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MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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static uint32_t
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get_addr(uint32_t addr, ems_t *p)
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{
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if (p && (scat_regs[SCAT_EMS_CTL] & 0x80) && (p->regs_2x9 & 0x80)) {
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addr = (addr & 0x3fff) | (((p->regs_2x9 & 3)<<8) | p->regs_2x8)<<14;
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}
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if (mem_size < 2048 &&
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((scat_regs[SCAT_DRAM_CONFIG] & 0x0F) > 7 ||
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(scat_regs[SCAT_EXT_BOUNDARY] & 0x40) != 0))
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addr = (addr & ~0x780000) | ((addr & 0x600000) >> 2);
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else
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if ((scat_regs[SCAT_DRAM_CONFIG] & 0x0F) < 8 &&
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(scat_regs[SCAT_EXT_BOUNDARY] & 0x40) == 0) {
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addr &= ~0x600000;
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if (mem_size > 2048 || (mem_size == 2048 &&
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(scat_regs[SCAT_DRAM_CONFIG] & 0x0F) < 6))
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addr |= (addr & 0x180000) << 2;
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}
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if ((scat_regs[SCAT_EXT_BOUNDARY] & 0x40) == 0 &&
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(scat_regs[SCAT_DRAM_CONFIG] & 0x0F) == 3 &&
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(addr & ~0x600000) >= 0x100000 && (addr & ~0x600000) < 0x160000)
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addr ^= mem_size < 2048 ? 0x1F0000 : 0x670000;
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return(addr);
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}
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static void
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memmap_state_update(void)
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{
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uint32_t addr;
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int i;
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for (i=16; i<24; i++) {
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addr = get_addr(0x40000 + (i<<14), NULL);
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mem_mapping_set_exec(&scat_top_mapping[i],
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addr < (mem_size<<10) ? ram+addr : NULL);
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}
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addr = get_addr(0xA0000, NULL);
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mem_mapping_set_exec(&scat_A000_mapping,
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addr < (mem_size<<10) ? ram+addr : NULL);
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for (i=0; i<6; i++) {
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addr = get_addr(0x100000 + (i<<16), NULL);
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mem_mapping_set_exec(&scat_shadowram_mapping[i],
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addr < (mem_size<<10) ? ram+addr : NULL);
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}
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flushmmucache();
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}
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static void
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ems_state(int state)
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{
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uint32_t base_addr, virt_addr;
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int i;
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for (i=0; i<32; i++) {
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base_addr = (i + 16) << 14;
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if (i >= 24)
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base_addr += 0x30000;
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if (state && (scat_ems[i].regs_2x9 & 0x80)) {
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virt_addr = get_addr(base_addr, &scat_ems[i]);
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if (i < 24)
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mem_mapping_disable(&scat_top_mapping[i]);
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mem_mapping_enable(&scat_mapping[i]);
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if (virt_addr < (mem_size<<10))
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mem_mapping_set_exec(&scat_mapping[i], ram+virt_addr);
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else
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mem_mapping_set_exec(&scat_mapping[i], NULL);
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} else {
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mem_mapping_set_exec(&scat_mapping[i], ram+base_addr);
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mem_mapping_disable(&scat_mapping[i]);
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if (i < 24)
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mem_mapping_enable(&scat_top_mapping[i]);
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}
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}
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}
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/* Read a byte from a LIM/EMS page. */
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static uint8_t
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ems_pgrd(uint32_t vaddr, void *priv)
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{
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ems_t *ems = (ems_t *)priv;
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uint32_t addr;
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uint8_t val = 0xff;
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addr = get_addr(vaddr, ems);
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if (addr < (mem_size << 10))
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val = mem_read_ram(addr, priv);
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#if SCAT_DEBUG > 1
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pclog("SCAT: ems_pgrd(%06x->%06x) = %02x\n", vaddr, addr, val);
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#endif
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return(val);
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}
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/* Write a byte to a LIM/EMS page. */
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static void
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ems_pgwr(uint32_t vaddr, uint8_t val, void *priv)
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{
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ems_t *ems = (ems_t *)priv;
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uint32_t addr;
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addr = get_addr(vaddr, ems);
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#if SCAT_DEBUG > 1
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pclog("SCAT: ems_pgwr(%06x->%06x, %02x)\n", vaddr, addr, val);
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#endif
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if (addr < (mem_size << 10))
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mem_write_ram(addr, val, priv);
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}
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/* Read from a LIM/EMS control register. */
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static uint8_t
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ems_read(uint16_t port, void *priv)
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{
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uint8_t val = 0xff;
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uint8_t idx;
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switch (port) {
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case 0x208:
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case 0x218:
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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idx = scat_ems_reg & 0x1f;
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val = scat_ems[idx].regs_2x8;
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}
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break;
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case 0x209:
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case 0x219:
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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idx = scat_ems_reg & 0x1f;
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val = scat_ems[idx].regs_2x9;
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}
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break;
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case 0x20A:
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case 0x21A:
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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val = scat_ems_reg;
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}
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break;
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}
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#if SCAT_DEBUG > 2
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pclog("SCAT: ems_read(%04x) = %02x\n", port, val);
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#endif
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return(val);
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}
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/* Write to one of the LIM/EMS control registers. */
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static void
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ems_write(uint16_t port, uint8_t val, void *priv)
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{
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uint32_t base_addr, virt_addr;
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uint8_t idx;
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#if SCAT_DEBUG > 1
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pclog("SCAT: ems_write(%04x, %02x)\n", port, val);
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#endif
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switch(port) {
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case 0x208:
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case 0x218:
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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idx = scat_ems_reg & 0x1f;
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scat_ems[idx].regs_2x8 = val;
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base_addr = (idx + 16) << 14;
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if (idx >= 24)
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base_addr += 0x30000;
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if ((scat_regs[SCAT_EMS_CTL] & 0x80) && (scat_ems[idx].regs_2x9 & 0x80)) {
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virt_addr = get_addr(base_addr, &scat_ems[idx]);
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if (virt_addr < (mem_size << 10))
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mem_mapping_set_exec(&scat_mapping[idx], ram + virt_addr);
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else
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mem_mapping_set_exec(&scat_mapping[idx], NULL);
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flushmmucache();
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}
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}
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break;
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case 0x209:
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case 0x219:
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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idx = scat_ems_reg & 0x1f;
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scat_ems[idx].regs_2x9 = val;
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base_addr = (idx + 16) << 14;
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if (idx >= 24)
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base_addr += 0x30000;
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if (scat_regs[SCAT_EMS_CTL] & 0x80) {
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if (val & 0x80) {
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virt_addr = get_addr(base_addr, &scat_ems[idx]);
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if (idx < 24)
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mem_mapping_disable(&scat_top_mapping[idx]);
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if (virt_addr < (mem_size << 10))
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mem_mapping_set_exec(&scat_mapping[idx], ram+virt_addr);
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else
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mem_mapping_set_exec(&scat_mapping[idx], NULL);
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mem_mapping_enable(&scat_mapping[idx]);
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} else {
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mem_mapping_set_exec(&scat_mapping[idx], ram + base_addr);
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mem_mapping_disable(&scat_mapping[idx]);
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if (idx < 24)
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mem_mapping_enable(&scat_top_mapping[idx]);
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}
|
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flushmmucache();
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}
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|
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if (scat_ems_reg & 0x80) {
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scat_ems_reg = (scat_ems_reg & 0xe0) | ((scat_ems_reg + 1) & 0x1f);
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}
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}
|
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break;
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|
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case 0x20A:
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case 0x21A:
|
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if ((scat_regs[SCAT_EMS_CTL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
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scat_ems_reg = val;
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}
|
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break;
|
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}
|
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}
|
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|
|
|
|
static uint8_t
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scat_read(uint16_t port, void *priv)
|
|
{
|
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uint8_t val = 0xff;
|
|
|
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switch (port) {
|
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case 0x23:
|
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switch (scat_index) {
|
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case SCAT_MISC_STATUS:
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val = (scat_regs[scat_index] & 0xbf) | ((mem_a20_key & 2) << 5);
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break;
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case SCAT_DRAM_CONFIG:
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val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
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break;
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case SCAT_SYS_CTL:
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val = port_92_read(0x0092, priv);
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break;
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default:
|
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val = scat_regs[scat_index];
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break;
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}
|
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break;
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|
|
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case 0x92:
|
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val = scat_regs[SCAT_SYS_CTL];
|
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break;
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}
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|
|
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#if SCAT_DEBUG > 2
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pclog("SCAT: read(%04x) = %02x\n", port, val);
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#endif
|
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return(val);
|
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}
|
|
|
|
|
|
/* Write to one of the Internal Control Registers. */
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static void
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ics_write(uint8_t idx, uint8_t val)
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{
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uint8_t reg_valid = 0;
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uint8_t shadow_update = 0;
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uint8_t map_update = 0;
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#if SCAT_DEBUG > 1
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pclog("SCAT: icr_write(%02x, %02x)\n", idx, val);
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#endif
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switch (idx) {
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case SCAT_CLOCK_CTL:
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case SCAT_PERIPH_CTL:
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reg_valid = 1;
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break;
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case SCAT_EMS_CTL:
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if (val & 0x40) {
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if (val & 1) {
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io_sethandler(0x0218, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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io_removehandler(0x0208, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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} else {
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io_sethandler(0x0208, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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io_removehandler(0x0218, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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}
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} else {
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io_removehandler(0x0208, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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io_removehandler(0x0218, 3,
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ems_read, NULL, NULL,
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ems_write, NULL, NULL, NULL);
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}
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ems_state(val & 0x80);
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reg_valid = 1;
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break;
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case SCAT_POWER_MGMT:
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val &= 0x40;
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reg_valid = 1;
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break;
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case SCAT_DRAM_CONFIG:
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if ((scat_regs[SCAT_EXT_BOUNDARY] & 0x40) == 0) {
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if ((val & 0x0f) == 3) {
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if (mem_size > 1024)
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mem_mapping_disable(&ram_high_mapping);
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for (idx=0; idx<6; idx++)
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mem_mapping_enable(&scat_shadowram_mapping[idx]);
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} else {
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for (idx=0; idx<6; idx++)
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mem_mapping_disable(&scat_shadowram_mapping[idx]);
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if (mem_size > 1024)
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mem_mapping_enable(&ram_high_mapping);
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}
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} else {
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for (idx=0; idx<6; idx++)
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mem_mapping_disable(&scat_shadowram_mapping[idx]);
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if (mem_size > 1024)
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mem_mapping_enable(&ram_high_mapping);
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}
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map_update = 1;
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cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
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cpu_update_waitstates();
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reg_valid = 1;
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break;
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case SCAT_EXT_BOUNDARY:
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set_xms_bound(val & 0x4f);
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mem_set_mem_state(0x40000, 0x60000,
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(val & 0x20) ? MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL : MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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if ((val ^ scat_regs[SCAT_EXT_BOUNDARY]) & 0x40)
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map_update = 1;
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reg_valid = 1;
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break;
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case SCAT_ROM_ENABLE:
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case SCAT_RAM_WR_PROTECT:
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case SCAT_SHADOW_RAM_EN_1:
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case SCAT_SHADOW_RAM_EN_2:
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case SCAT_SHADOW_RAM_EN_3:
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reg_valid = 1;
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shadow_update = 1;
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break;
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case SCAT_SYS_CTL:
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port_92_write(0x0092, val, NULL);
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break;
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default:
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break;
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}
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if (reg_valid)
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scat_regs[scat_index] = val;
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#ifndef RELEASE_BUILD
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else
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pclog("SCAT: attemped write to register %02X at %04X:%04X\n",
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idx, val, CS, cpu_state.pc);
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#endif
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if (shadow_update)
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shadow_state_update();
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if (map_update)
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memmap_state_update();
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}
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static void
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scat_write(uint16_t port, uint8_t val, void *priv)
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{
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#if SCAT_DEBUG > 2
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pclog("SCAT: write(%04x, %02x)\n", port, val);
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#endif
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switch (port) {
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case 0x22:
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scat_index = val;
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break;
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case 0x23:
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ics_write(scat_index, val);
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break;
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}
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}
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static void
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scat_init(void)
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{
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int i;
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#if SCAT_DEBUG
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pclog("SCAT: initializing..\n");
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#endif
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io_sethandler(0x0022, 2,
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scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
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port_92_reset();
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port_92_add();
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for (i=0; i<128; i++)
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scat_regs[i] = 0xff;
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scat_regs[SCAT_DMA_WS_CTL] = 0x00;
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scat_regs[SCAT_VERSION] = 0x0a;
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scat_regs[SCAT_CLOCK_CTL] = 0x02;
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scat_regs[SCAT_PERIPH_CTL] = 0x80;
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scat_regs[SCAT_MISC_STATUS] = 0x37;
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scat_regs[SCAT_POWER_MGMT] = 0x00;
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scat_regs[SCAT_ROM_ENABLE] = 0xC0;
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scat_regs[SCAT_RAM_WR_PROTECT] = 0x00;
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scat_regs[SCAT_SHADOW_RAM_EN_1] = 0x00;
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scat_regs[SCAT_SHADOW_RAM_EN_2] = 0x00;
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scat_regs[SCAT_SHADOW_RAM_EN_3] = 0x00;
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scat_regs[SCAT_DRAM_CONFIG] = cpu_waitstates == 1 ? 0x00 : 0x10;
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scat_regs[SCAT_EXT_BOUNDARY] = 0x00;
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scat_regs[SCAT_EMS_CTL] = 0x00;
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scat_regs[SCAT_SYS_CTL] = 0x00;
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/* Limit RAM size to 16MB. */
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mem_mapping_set_addr(&ram_low_mapping, 0x000000, 0x40000);
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/*
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* Configure the DRAM controller.
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*
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* Since SCAT allows mixing of the various-sized DRAM chips,
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* memory configuration is not simple. The SCAT datasheet
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* tells us in table 6-6 how to set up the four banks:
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*
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* MEM SIZE MIX_EN RAMCFG Ext RAM Comments
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* 0 K 0 0x00 No RAM installed
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* 512 K 0 0x01 0 K
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* 640 K 0 0x02 0 K
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* 1 M 0 0x03 384K
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* 1 M 0 0x04 0 K
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* 1.5 M 0 0x05 512K
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* 2 M 0 0x06 1 M 4x512K
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* 2 M 0 0x08 1 M 1x2M
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* 2.5 M 1 0x01 1.5M 2M+512K
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* 3 M 1 0x04 2 M 1x2M
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* 4 M 0 0x09 3 M 2x2M
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* 4.5 M 1 0x02 3.5M 2x2M+512K
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* 5 M 1 0x05 4 M 2x2M+2x512K
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* 6 M 0 0x0a 5 M 3x2M
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* 6.5 M 1 0x03 5.5M 3x2M+512K
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* 8 M 0 0x0b 7 M 4x2M
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*/
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pclog("SCAT: mem_size=%d\n", mem_size);
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/* Create the 32 EMS page frame mappings for 256-640K. */
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for (i=0; i<24; i++) {
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mem_mapping_add(&scat_top_mapping[i],
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0x40000 + (i<<14), 0x4000,
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ems_pgrd, NULL, NULL,
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ems_pgwr, NULL, NULL,
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mem_size > 256+(i<<4) ? ram+0x40000+(i<<14) : NULL,
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MEM_MAPPING_INTERNAL, NULL);
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mem_mapping_enable(&scat_top_mapping[i]);
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}
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/* Re-map the 128K at A0000 (video BIOS) to above 16MB+top. */
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mem_mapping_add(&scat_A000_mapping,
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0xA0000, 0x20000,
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ems_pgrd, NULL, NULL,
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ems_pgwr, NULL, NULL,
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ram+0xA0000,
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MEM_MAPPING_INTERNAL, NULL);
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mem_mapping_disable(&scat_A000_mapping);
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/* Create 32 page frames for EMS, each 16K. */
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for (i=0; i<32; i++) {
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scat_ems[i].regs_2x8 = 0xff;
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scat_ems[i].regs_2x9 = 0x03;
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mem_mapping_add(&scat_mapping[i],
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(i + (i >= 24 ? 28 : 16)) << 14, 0x04000,
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ems_pgrd, NULL, NULL,
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ems_pgwr, NULL, NULL,
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ram + ((i + (i >= 24 ? 28 : 16)) << 14),
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0, &scat_ems[i]);
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mem_mapping_disable(&scat_mapping[i]);
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}
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|
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for (i=4; i<10; i++) isram[i] = 0;
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|
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/* Re-map the BIOS ROM (C0000-FFFFF) area. */
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for (i=12; i<16; i++) {
|
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mem_mapping_add(&scat_high_mapping[i],
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(i<<14) + 0xFC0000, 0x04000,
|
|
mem_read_bios, mem_read_biosw, mem_read_biosl,
|
|
mem_write_null, mem_write_nullw, mem_write_nulll,
|
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rom+(i<<14),
|
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0, NULL);
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}
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for (i=0; i<6; i++) {
|
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mem_mapping_add(&scat_shadowram_mapping[i],
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0x100000 + (i<<16), 0x10000,
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ems_pgrd, NULL, NULL,
|
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ems_pgwr, NULL, NULL,
|
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mem_size >= 1024 ? ram+get_addr(0x100000+(i<<16), NULL) : NULL,
|
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MEM_MAPPING_INTERNAL, NULL);
|
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}
|
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|
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set_xms_bound(0);
|
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shadow_state_update();
|
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}
|
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|
|
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void
|
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machine_at_scat_init(machine_t *model)
|
|
{
|
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machine_at_init(model);
|
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device_add(&fdc_at_device);
|
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|
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scat_init();
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}
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