885 lines
41 KiB
C
885 lines
41 KiB
C
#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include <math.h>
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#ifndef INFINITY
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# define INFINITY (__builtin_inff())
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#endif
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#define HAVE_STDARG_H
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#include "../86box.h"
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#include "cpu.h"
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#include "x86.h"
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#include "x86_ops.h"
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#include "x87.h"
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#include "../io.h"
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#include "../mem.h"
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#include "../nmi.h"
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#include "../pic.h"
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#include "../timer.h"
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#include "../floppy/fdd.h"
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#include "../floppy/fdc.h"
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#ifdef USE_DYNAREC
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#include "codegen.h"
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#include "codegen_backend.h"
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#endif
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#include "386_common.h"
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#ifdef ENABLE_386_DYNAREC_LOG
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int x386_dynarec_do_log = ENABLE_386_DYNAREC_LOG;
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void
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x386_dynarec_log(const char *fmt, ...)
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{
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va_list ap;
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if (x386_dynarec_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define x386_dynarec_log(fmt, ...)
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#endif
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#define CPU_BLOCK_END() cpu_block_end = 1
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int inrecomp = 0;
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int cpu_recomp_blocks, cpu_recomp_full_ins, cpu_new_blocks;
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int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, cpu_recomp_full_ins_latched, cpu_new_blocks_latched;
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int cpu_block_end = 0;
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static __inline void fetch_ea_32_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = cpu_state.ea_seg->base;
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if (cpu_rm == 4)
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{
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uint8_t sib = rmdat >> 8;
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switch (cpu_mod)
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{
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case 0:
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cpu_state.eaaddr = cpu_state.regs[sib & 7].l;
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cpu_state.pc++;
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break;
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case 1:
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cpu_state.pc++;
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cpu_state.eaaddr = ((uint32_t)(int8_t)getbyte()) + cpu_state.regs[sib & 7].l;
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break;
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case 2:
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cpu_state.eaaddr = (fastreadl(cs + cpu_state.pc + 1)) + cpu_state.regs[sib & 7].l;
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cpu_state.pc += 5;
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break;
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}
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/*SIB byte present*/
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if ((sib & 7) == 5 && !cpu_mod)
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cpu_state.eaaddr = getlong();
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else if ((sib & 6) == 4 && !cpu_state.ssegs)
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{
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easeg = ss;
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cpu_state.ea_seg = &cpu_state.seg_ss;
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}
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if (((sib >> 3) & 7) != 4)
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cpu_state.eaaddr += cpu_state.regs[(sib >> 3) & 7].l << (sib >> 6);
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}
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else
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{
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cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
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if (cpu_mod)
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{
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if (cpu_rm == 5 && !cpu_state.ssegs)
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{
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easeg = ss;
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cpu_state.ea_seg = &cpu_state.seg_ss;
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}
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if (cpu_mod == 1)
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{
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cpu_state.eaaddr += ((uint32_t)(int8_t)(rmdat >> 8));
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cpu_state.pc++;
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}
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else
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{
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cpu_state.eaaddr += getlong();
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}
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}
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else if (cpu_rm == 5)
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{
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cpu_state.eaaddr = getlong();
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}
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}
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
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}
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cpu_state.last_ea = cpu_state.eaaddr;
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}
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static __inline void fetch_ea_16_long(uint32_t rmdat)
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{
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eal_r = eal_w = NULL;
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easeg = cpu_state.ea_seg->base;
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if (!cpu_mod && cpu_rm == 6)
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{
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cpu_state.eaaddr = getword();
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}
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else
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{
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switch (cpu_mod)
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{
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case 0:
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cpu_state.eaaddr = 0;
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break;
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case 1:
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cpu_state.eaaddr = (uint16_t)(int8_t)(rmdat >> 8); cpu_state.pc++;
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break;
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case 2:
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cpu_state.eaaddr = getword();
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break;
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}
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cpu_state.eaaddr += (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
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if (mod1seg[cpu_rm] == &ss && !cpu_state.ssegs)
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{
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easeg = ss;
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cpu_state.ea_seg = &cpu_state.seg_ss;
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}
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cpu_state.eaaddr &= 0xFFFF;
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}
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if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
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{
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uint32_t addr = easeg + cpu_state.eaaddr;
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if ( readlookup2[addr >> 12] != -1)
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eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
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if (writelookup2[addr >> 12] != -1)
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eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
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}
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cpu_state.last_ea = cpu_state.eaaddr;
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}
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#define fetch_ea_16(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_16_long(rmdat); if (cpu_state.abrt) return 1; }
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#define fetch_ea_32(rmdat) cpu_state.pc++; cpu_mod=(rmdat >> 6) & 3; cpu_reg=(rmdat >> 3) & 7; cpu_rm = rmdat & 7; if (cpu_mod != 3) { fetch_ea_32_long(rmdat); } if (cpu_state.abrt) return 1
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#include "x86_flags.h"
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/*Prefetch emulation is a fairly simplistic model:
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- All instruction bytes must be fetched before it starts.
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- Cycles used for non-instruction memory accesses are counted and subtracted
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from the total cycles taken
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- Any remaining cycles are used to refill the prefetch queue.
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Note that this is only used for 286 / 386 systems. It is disabled when the
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internal cache on 486+ CPUs is enabled.
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*/
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static int prefetch_bytes = 0;
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static int prefetch_prefixes = 0;
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static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int reads_l, int writes, int writes_l, int ea32)
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{
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int mem_cycles = reads*cpu_cycles_read + reads_l*cpu_cycles_read_l + writes*cpu_cycles_write + writes_l*cpu_cycles_write_l;
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if (instr_cycles < mem_cycles)
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instr_cycles = mem_cycles;
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prefetch_bytes -= prefetch_prefixes;
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prefetch_bytes -= bytes;
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if (modrm != -1)
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{
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if (ea32)
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{
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if ((modrm & 7) == 4)
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{
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if ((modrm & 0x700) == 0x500)
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prefetch_bytes -= 5;
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else if ((modrm & 0xc0) == 0x40)
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prefetch_bytes -= 2;
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else if ((modrm & 0xc0) == 0x80)
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prefetch_bytes -= 5;
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}
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else
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{
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if ((modrm & 0xc7) == 0x05)
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prefetch_bytes -= 4;
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else if ((modrm & 0xc0) == 0x40)
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prefetch_bytes--;
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else if ((modrm & 0xc0) == 0x80)
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prefetch_bytes -= 4;
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}
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}
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else
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{
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if ((modrm & 0xc7) == 0x06)
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prefetch_bytes -= 2;
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else if ((modrm & 0xc0) != 0xc0)
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prefetch_bytes -= ((modrm & 0xc0) >> 6);
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}
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}
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/* Fill up prefetch queue */
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while (prefetch_bytes < 0)
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{
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prefetch_bytes += cpu_prefetch_width;
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cycles -= cpu_prefetch_cycles;
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}
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/* Subtract cycles used for memory access by instruction */
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instr_cycles -= mem_cycles;
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while (instr_cycles >= cpu_prefetch_cycles)
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{
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prefetch_bytes += cpu_prefetch_width;
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instr_cycles -= cpu_prefetch_cycles;
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}
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prefetch_prefixes = 0;
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if (prefetch_bytes > 16)
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prefetch_bytes = 16;
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}
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static void prefetch_flush()
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{
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prefetch_bytes = 0;
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}
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#define PREFETCH_RUN(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32) \
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do { if (cpu_prefetch_cycles) prefetch_run(instr_cycles, bytes, modrm, reads, reads_l, writes, writes_l, ea32); } while (0)
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#define PREFETCH_PREFIX() do { if (cpu_prefetch_cycles) prefetch_prefixes++; } while (0)
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#define PREFETCH_FLUSH() prefetch_flush()
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void enter_smm()
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{
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uint32_t smram_state = smbase + 0xfe00;
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uint32_t old_cr0 = cr0;
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uint32_t old_flags = cpu_state.flags | ((uint32_t)cpu_state.eflags << 16);
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cr0 &= ~0x8000000d;
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cpu_state.flags = 2;
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cpu_state.eflags = 0;
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in_smm = 1;
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smi_latched = 1;
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mem_writel_phys(smram_state + 0xf8, smbase);
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mem_writel_phys(smram_state + 0x128, cr4);
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mem_writel_phys(smram_state + 0x130, cpu_state.seg_es.limit);
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mem_writel_phys(smram_state + 0x134, cpu_state.seg_es.base);
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mem_writel_phys(smram_state + 0x138, cpu_state.seg_es.access);
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mem_writel_phys(smram_state + 0x13c, cpu_state.seg_cs.limit);
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mem_writel_phys(smram_state + 0x140, cpu_state.seg_cs.base);
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mem_writel_phys(smram_state + 0x144, cpu_state.seg_cs.access);
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mem_writel_phys(smram_state + 0x148, cpu_state.seg_ss.limit);
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mem_writel_phys(smram_state + 0x14c, cpu_state.seg_ss.base);
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mem_writel_phys(smram_state + 0x150, cpu_state.seg_ss.access);
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mem_writel_phys(smram_state + 0x154, cpu_state.seg_ds.limit);
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mem_writel_phys(smram_state + 0x158, cpu_state.seg_ds.base);
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mem_writel_phys(smram_state + 0x15c, cpu_state.seg_ds.access);
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mem_writel_phys(smram_state + 0x160, cpu_state.seg_fs.limit);
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mem_writel_phys(smram_state + 0x164, cpu_state.seg_fs.base);
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mem_writel_phys(smram_state + 0x168, cpu_state.seg_fs.access);
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mem_writel_phys(smram_state + 0x16c, cpu_state.seg_gs.limit);
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mem_writel_phys(smram_state + 0x170, cpu_state.seg_gs.base);
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mem_writel_phys(smram_state + 0x174, cpu_state.seg_gs.access);
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mem_writel_phys(smram_state + 0x178, ldt.limit);
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mem_writel_phys(smram_state + 0x17c, ldt.base);
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mem_writel_phys(smram_state + 0x180, ldt.access);
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mem_writel_phys(smram_state + 0x184, gdt.limit);
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mem_writel_phys(smram_state + 0x188, gdt.base);
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mem_writel_phys(smram_state + 0x18c, gdt.access);
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mem_writel_phys(smram_state + 0x190, idt.limit);
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mem_writel_phys(smram_state + 0x194, idt.base);
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mem_writel_phys(smram_state + 0x198, idt.access);
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mem_writel_phys(smram_state + 0x19c, tr.limit);
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mem_writel_phys(smram_state + 0x1a0, tr.base);
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mem_writel_phys(smram_state + 0x1a4, tr.access);
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mem_writel_phys(smram_state + 0x1a8, cpu_state.seg_es.seg);
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mem_writel_phys(smram_state + 0x1ac, cpu_state.seg_cs.seg);
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mem_writel_phys(smram_state + 0x1b0, cpu_state.seg_ss.seg);
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mem_writel_phys(smram_state + 0x1b4, cpu_state.seg_ds.seg);
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mem_writel_phys(smram_state + 0x1b8, cpu_state.seg_fs.seg);
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mem_writel_phys(smram_state + 0x1bc, cpu_state.seg_gs.seg);
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mem_writel_phys(smram_state + 0x1c0, ldt.seg);
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mem_writel_phys(smram_state + 0x1c4, tr.seg);
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mem_writel_phys(smram_state + 0x1c8, dr[7]);
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mem_writel_phys(smram_state + 0x1cc, dr[6]);
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mem_writel_phys(smram_state + 0x1d0, EAX);
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mem_writel_phys(smram_state + 0x1d4, ECX);
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mem_writel_phys(smram_state + 0x1d8, EDX);
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mem_writel_phys(smram_state + 0x1dc, EBX);
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mem_writel_phys(smram_state + 0x1e0, ESP);
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mem_writel_phys(smram_state + 0x1e4, EBP);
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mem_writel_phys(smram_state + 0x1e8, ESI);
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mem_writel_phys(smram_state + 0x1ec, EDI);
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mem_writel_phys(smram_state + 0x1f0, cpu_state.pc);
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mem_writel_phys(smram_state + 0x1d0, old_flags);
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mem_writel_phys(smram_state + 0x1f8, cr3);
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mem_writel_phys(smram_state + 0x1fc, old_cr0);
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ds = es = fs_seg = gs = ss = 0;
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DS = ES = FS = GS = SS = 0;
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cpu_state.seg_ds.limit = cpu_state.seg_es.limit = cpu_state.seg_fs.limit = cpu_state.seg_gs.limit
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= cpu_state.seg_ss.limit = 0xffffffff;
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cpu_state.seg_ds.limit_high = cpu_state.seg_es.limit_high = cpu_state.seg_fs.limit_high
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= cpu_state.seg_gs.limit_high = cpu_state.seg_ss.limit_high = 0xffffffff;
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cpu_state.seg_ds.limit_low = cpu_state.seg_es.limit_low = cpu_state.seg_fs.limit_low
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= cpu_state.seg_gs.limit_low = cpu_state.seg_ss.limit_low = 0;
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cpu_state.seg_ds.access = cpu_state.seg_es.access = cpu_state.seg_fs.access
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= cpu_state.seg_gs.access = cpu_state.seg_ss.access = 0x93;
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cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked
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= cpu_state.seg_gs.checked = cpu_state.seg_ss.checked = 1;
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CS = 0x3000;
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cs = smbase;
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cpu_state.seg_cs.limit = cpu_state.seg_cs.limit_high = 0xffffffff;
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cpu_state.seg_cs.limit_low = 0;
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cpu_state.seg_cs.access = 0x93;
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cpu_state.seg_cs.checked = 1;
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cr4 = 0;
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dr[7] = 0x400;
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cpu_state.pc = 0x8000;
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nmi_mask = 0;
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}
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void leave_smm()
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{
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uint32_t smram_state = smbase + 0xfe00;
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smbase = mem_readl_phys(smram_state + 0xf8);
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cr4 = mem_readl_phys(smram_state + 0x128);
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cpu_state.seg_es.limit = cpu_state.seg_es.limit_high = mem_readl_phys(smram_state + 0x130);
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cpu_state.seg_es.base = mem_readl_phys(smram_state + 0x134);
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cpu_state.seg_es.limit_low = cpu_state.seg_es.base;
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cpu_state.seg_es.access = mem_readl_phys(smram_state + 0x138);
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cpu_state.seg_cs.limit = cpu_state.seg_cs.limit_high = mem_readl_phys(smram_state + 0x13c);
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cpu_state.seg_cs.base = mem_readl_phys(smram_state + 0x140);
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cpu_state.seg_cs.limit_low = cpu_state.seg_cs.base;
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cpu_state.seg_cs.access = mem_readl_phys(smram_state + 0x144);
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cpu_state.seg_ss.limit = cpu_state.seg_ss.limit_high = mem_readl_phys(smram_state + 0x148);
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cpu_state.seg_ss.base = mem_readl_phys(smram_state + 0x14c);
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cpu_state.seg_ss.limit_low = cpu_state.seg_ss.base;
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cpu_state.seg_ss.access = mem_readl_phys(smram_state + 0x150);
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cpu_state.seg_ds.limit = cpu_state.seg_ds.limit_high = mem_readl_phys(smram_state + 0x154);
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cpu_state.seg_ds.base = mem_readl_phys(smram_state + 0x158);
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cpu_state.seg_ds.limit_low = cpu_state.seg_ds.base;
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cpu_state.seg_ds.access = mem_readl_phys(smram_state + 0x15c);
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cpu_state.seg_fs.limit = cpu_state.seg_fs.limit_high = mem_readl_phys(smram_state + 0x160);
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cpu_state.seg_fs.base = mem_readl_phys(smram_state + 0x164);
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cpu_state.seg_fs.limit_low = cpu_state.seg_fs.base;
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cpu_state.seg_fs.access = mem_readl_phys(smram_state + 0x168);
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cpu_state.seg_gs.limit = cpu_state.seg_gs.limit_high = mem_readl_phys(smram_state + 0x16c);
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cpu_state.seg_gs.base = mem_readl_phys(smram_state + 0x170);
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cpu_state.seg_gs.limit_low = cpu_state.seg_gs.base;
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cpu_state.seg_gs.access = mem_readl_phys(smram_state + 0x174);
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ldt.limit = ldt.limit_high = mem_readl_phys(smram_state + 0x178);
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ldt.base = mem_readl_phys(smram_state + 0x17c);
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ldt.limit_low = ldt.base;
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ldt.access = mem_readl_phys(smram_state + 0x180);
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gdt.limit = gdt.limit_high = mem_readl_phys(smram_state + 0x184);
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gdt.base = mem_readl_phys(smram_state + 0x188);
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gdt.limit_low = gdt.base;
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gdt.access = mem_readl_phys(smram_state + 0x18c);
|
|
|
|
idt.limit = idt.limit_high = mem_readl_phys(smram_state + 0x190);
|
|
idt.base = mem_readl_phys(smram_state + 0x194);
|
|
idt.limit_low = idt.base;
|
|
idt.access = mem_readl_phys(smram_state + 0x198);
|
|
|
|
tr.limit = tr.limit_high = mem_readl_phys(smram_state + 0x19c);
|
|
tr.base = mem_readl_phys(smram_state + 0x1a0);
|
|
tr.limit_low = tr.base;
|
|
tr.access = mem_readl_phys(smram_state + 0x1a4);
|
|
|
|
ES = mem_readl_phys(smram_state + 0x1a8);
|
|
CS = mem_readl_phys(smram_state + 0x1ac);
|
|
SS = mem_readl_phys(smram_state + 0x1b0);
|
|
DS = mem_readl_phys(smram_state + 0x1b4);
|
|
FS = mem_readl_phys(smram_state + 0x1b8);
|
|
GS = mem_readl_phys(smram_state + 0x1bc);
|
|
ldt.seg = mem_readl_phys(smram_state + 0x1c0);
|
|
tr.seg = mem_readl_phys(smram_state + 0x1c4);
|
|
|
|
dr[7] = mem_readl_phys(smram_state + 0x1c8);
|
|
dr[6] = mem_readl_phys(smram_state + 0x1cc);
|
|
EAX = mem_readl_phys(smram_state + 0x1d0);
|
|
ECX = mem_readl_phys(smram_state + 0x1d4);
|
|
EDX = mem_readl_phys(smram_state + 0x1d8);
|
|
EBX = mem_readl_phys(smram_state + 0x1dc);
|
|
ESP = mem_readl_phys(smram_state + 0x1e0);
|
|
EBP = mem_readl_phys(smram_state + 0x1e4);
|
|
ESI = mem_readl_phys(smram_state + 0x1e8);
|
|
EDI = mem_readl_phys(smram_state + 0x1ec);
|
|
|
|
cpu_state.pc = mem_readl_phys(smram_state + 0x1f0);
|
|
uint32_t new_flags = mem_readl_phys(smram_state + 0x1f4);
|
|
cpu_state.flags = new_flags & 0xffff;
|
|
cpu_state.eflags = new_flags >> 16;
|
|
cr3 = mem_readl_phys(smram_state + 0x1f8);
|
|
cr0 = mem_readl_phys(smram_state + 0x1fc);
|
|
|
|
cpu_state.seg_cs.access &= ~0x60;
|
|
cpu_state.seg_cs.access |= cpu_state.seg_ss.access & 0x60; //cpl is dpl of ss
|
|
|
|
if((cr0 & 1) && !(cpu_state.eflags&VM_FLAG))
|
|
{
|
|
cpu_state.seg_cs.checked = CS ? 1 : 0;
|
|
cpu_state.seg_ds.checked = DS ? 1 : 0;
|
|
cpu_state.seg_es.checked = ES ? 1 : 0;
|
|
cpu_state.seg_fs.checked = FS ? 1 : 0;
|
|
cpu_state.seg_gs.checked = GS ? 1 : 0;
|
|
cpu_state.seg_ss.checked = SS ? 1 : 0;
|
|
}
|
|
else
|
|
{
|
|
cpu_state.seg_cs.checked = cpu_state.seg_ds.checked = cpu_state.seg_es.checked
|
|
= cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = cpu_state.seg_ss.checked = 1;
|
|
}
|
|
|
|
in_smm = 0;
|
|
|
|
nmi_mask = 1;
|
|
}
|
|
|
|
#define OP_TABLE(name) ops_ ## name
|
|
#define CLOCK_CYCLES(c) cycles -= (c)
|
|
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
|
|
|
|
#include "386_ops.h"
|
|
|
|
#define CACHE_ON() (!(cr0 & (1 << 30)) && !(cpu_state.flags & T_FLAG))
|
|
|
|
#ifdef USE_DYNAREC
|
|
static int cycles_main = 0;
|
|
|
|
|
|
void exec386_dynarec(int cycs)
|
|
{
|
|
int vector;
|
|
uint32_t addr;
|
|
int tempi;
|
|
int cycdiff;
|
|
int oldcyc;
|
|
int cyc_period = cycs / 2000; /*5us*/
|
|
|
|
cycles_main += cycs;
|
|
while (cycles_main > 0)
|
|
{
|
|
int cycles_start;
|
|
|
|
cycles += cyc_period;
|
|
cycles_start = cycles;
|
|
|
|
while (cycles>0)
|
|
{
|
|
oldcyc=cycles;
|
|
if (!CACHE_ON()) /*Interpret block*/
|
|
{
|
|
cpu_block_end = 0;
|
|
x86_was_reset = 0;
|
|
while (!cpu_block_end)
|
|
{
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &cpu_state.seg_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
|
|
if (!cpu_state.abrt)
|
|
{
|
|
uint8_t opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
trap = cpu_state.flags & T_FLAG;
|
|
|
|
cpu_state.pc++;
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
}
|
|
|
|
if (((cs + cpu_state.pc) >> 12) != pccache)
|
|
CPU_BLOCK_END();
|
|
|
|
if (in_smm && smi_line && is_pentium)
|
|
CPU_BLOCK_END();
|
|
|
|
if (cpu_state.abrt)
|
|
CPU_BLOCK_END();
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
ins++;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
uint32_t phys_addr = get_phys(cs+cpu_state.pc);
|
|
int hash = HASH(phys_addr);
|
|
codeblock_t *block = &codeblock[codeblock_hash[hash]];
|
|
int valid_block = 0;
|
|
|
|
if (!cpu_state.abrt)
|
|
{
|
|
page_t *page = &pages[phys_addr >> 12];
|
|
|
|
/*Block must match current CS, PC, code segment size,
|
|
and physical address. The physical address check will
|
|
also catch any page faults at this stage*/
|
|
valid_block = (block->pc == cs + cpu_state.pc) && (block->_cs == cs) &&
|
|
(block->phys == phys_addr) && !((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
|
|
((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
|
|
if (!valid_block)
|
|
{
|
|
uint64_t mask = (uint64_t)1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
|
|
int byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
|
|
uint64_t byte_mask = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
|
|
|
|
if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
|
|
{
|
|
/*Walk page tree to see if we find the correct block*/
|
|
codeblock_t *new_block = codeblock_tree_find(phys_addr, cs);
|
|
if (new_block)
|
|
{
|
|
valid_block = (new_block->pc == cs + cpu_state.pc) && (new_block->_cs == cs) &&
|
|
(new_block->phys == phys_addr) && !((new_block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
|
|
((new_block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK));
|
|
if (valid_block)
|
|
{
|
|
block = new_block;
|
|
codeblock_hash[hash] = get_block_nr(block);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (valid_block && (block->page_mask & *block->dirty_mask))
|
|
{
|
|
codegen_check_flush(page, page->dirty_mask, phys_addr);
|
|
if (block->pc == BLOCK_PC_INVALID)
|
|
valid_block = 0;
|
|
else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
|
|
block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
|
|
}
|
|
if (valid_block && block->page_mask2)
|
|
{
|
|
/*We don't want the second page to cause a page
|
|
fault at this stage - that would break any
|
|
code crossing a page boundary where the first
|
|
page is present but the second isn't. Instead
|
|
allow the first page to be interpreted and for
|
|
the page fault to occur when the page boundary
|
|
is actually crossed.*/
|
|
uint32_t phys_addr_2 = get_phys_noabrt(block->pc + ((block->flags & CODEBLOCK_BYTE_MASK) ? 0x40 : 0x400));
|
|
page_t *page_2 = &pages[phys_addr_2 >> 12];
|
|
if ((block->phys_2 ^ phys_addr_2) & ~0xfff)
|
|
valid_block = 0;
|
|
else if (block->page_mask2 & *block->dirty_mask2)
|
|
{
|
|
codegen_check_flush(page_2, page_2->dirty_mask, phys_addr_2);
|
|
if (block->pc == BLOCK_PC_INVALID)
|
|
valid_block = 0;
|
|
else if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
|
|
block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
|
|
}
|
|
}
|
|
if (valid_block && (block->flags & CODEBLOCK_IN_DIRTY_LIST))
|
|
{
|
|
block->flags &= ~CODEBLOCK_WAS_RECOMPILED;
|
|
if (block->flags & CODEBLOCK_BYTE_MASK)
|
|
block->flags |= CODEBLOCK_NO_IMMEDIATES;
|
|
else
|
|
block->flags |= CODEBLOCK_BYTE_MASK;
|
|
}
|
|
if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED) && (block->flags & CODEBLOCK_STATIC_TOP) && block->TOP != (cpu_state.TOP & 7))
|
|
{
|
|
/*FPU top-of-stack does not match the value this block was compiled
|
|
with, re-compile using dynamic top-of-stack*/
|
|
block->flags &= ~(CODEBLOCK_STATIC_TOP | CODEBLOCK_WAS_RECOMPILED);
|
|
}
|
|
}
|
|
|
|
if (valid_block && (block->flags & CODEBLOCK_WAS_RECOMPILED))
|
|
{
|
|
void (*code)() = (void *)&block->data[BLOCK_START];
|
|
|
|
inrecomp=1;
|
|
code();
|
|
inrecomp=0;
|
|
|
|
cpu_recomp_blocks++;
|
|
}
|
|
else if (valid_block && !cpu_state.abrt)
|
|
{
|
|
uint32_t start_pc = cs+cpu_state.pc;
|
|
const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
|
|
|
|
cpu_block_end = 0;
|
|
x86_was_reset = 0;
|
|
|
|
cpu_new_blocks++;
|
|
|
|
codegen_block_start_recompile(block);
|
|
codegen_in_recompile = 1;
|
|
|
|
while (!cpu_block_end)
|
|
{
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &cpu_state.seg_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
|
|
if (!cpu_state.abrt)
|
|
{
|
|
uint8_t opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
|
|
trap = cpu_state.flags & T_FLAG;
|
|
|
|
cpu_state.pc++;
|
|
|
|
codegen_generate_call(opcode, x86_opcodes[(opcode | cpu_state.op32) & 0x3ff], fetchdat, cpu_state.pc, cpu_state.pc-1);
|
|
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
|
|
if (x86_was_reset)
|
|
break;
|
|
}
|
|
|
|
/*Cap source code at 4000 bytes per block; this
|
|
will prevent any block from spanning more than
|
|
2 pages. In practice this limit will never be
|
|
hit, as host block size is only 2kB*/
|
|
if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
|
|
CPU_BLOCK_END();
|
|
|
|
if (in_smm && smi_line && is_pentium)
|
|
CPU_BLOCK_END();
|
|
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
codegen_block_remove();
|
|
CPU_BLOCK_END();
|
|
}
|
|
|
|
ins++;
|
|
}
|
|
|
|
if (!cpu_state.abrt && !x86_was_reset)
|
|
codegen_block_end_recompile(block);
|
|
|
|
if (x86_was_reset)
|
|
codegen_reset();
|
|
|
|
codegen_in_recompile = 0;
|
|
}
|
|
else if (!cpu_state.abrt)
|
|
{
|
|
/*Mark block but do not recompile*/
|
|
uint32_t start_pc = cs+cpu_state.pc;
|
|
const int max_block_size = (block->flags & CODEBLOCK_BYTE_MASK) ? ((128 - 25) - (start_pc & 0x3f)) : 1000;
|
|
|
|
cpu_block_end = 0;
|
|
x86_was_reset = 0;
|
|
|
|
codegen_block_init(phys_addr);
|
|
|
|
while (!cpu_block_end)
|
|
{
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
cpu_state.op32 = use32;
|
|
|
|
cpu_state.ea_seg = &cpu_state.seg_ds;
|
|
cpu_state.ssegs = 0;
|
|
|
|
codegen_endpc = (cs + cpu_state.pc) + 8;
|
|
fetchdat = fastreadl(cs + cpu_state.pc);
|
|
|
|
if (!cpu_state.abrt)
|
|
{
|
|
uint8_t opcode = fetchdat & 0xFF;
|
|
fetchdat >>= 8;
|
|
|
|
trap = cpu_state.flags & T_FLAG;
|
|
|
|
cpu_state.pc++;
|
|
|
|
x86_opcodes[(opcode | cpu_state.op32) & 0x3ff](fetchdat);
|
|
|
|
if (x86_was_reset)
|
|
break;
|
|
}
|
|
|
|
/*Cap source code at 4000 bytes per block; this
|
|
will prevent any block from spanning more than
|
|
2 pages. In practice this limit will never be
|
|
hit, as host block size is only 2kB*/
|
|
if (((cs+cpu_state.pc) - start_pc) >= max_block_size)
|
|
CPU_BLOCK_END();
|
|
|
|
if (in_smm && smi_line && is_pentium)
|
|
CPU_BLOCK_END();
|
|
|
|
if (trap)
|
|
CPU_BLOCK_END();
|
|
|
|
if (nmi && nmi_enable && nmi_mask)
|
|
CPU_BLOCK_END();
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
codegen_block_remove();
|
|
CPU_BLOCK_END();
|
|
}
|
|
|
|
ins++;
|
|
}
|
|
|
|
if (!cpu_state.abrt && !x86_was_reset)
|
|
codegen_block_end();
|
|
|
|
if (x86_was_reset)
|
|
codegen_reset();
|
|
}
|
|
else
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
|
|
}
|
|
|
|
cycdiff=oldcyc-cycles;
|
|
tsc += cycdiff;
|
|
|
|
if (cpu_state.abrt)
|
|
{
|
|
flags_rebuild();
|
|
tempi = cpu_state.abrt;
|
|
cpu_state.abrt = 0;
|
|
x86_doabrt(tempi);
|
|
if (cpu_state.abrt)
|
|
{
|
|
cpu_state.abrt = 0;
|
|
cpu_state.pc = cpu_state.oldpc;
|
|
x386_dynarec_log("Double fault %i\n", ins);
|
|
pmodeint(8, 0);
|
|
if (cpu_state.abrt)
|
|
{
|
|
cpu_state.abrt = 0;
|
|
softresetx86();
|
|
cpu_set_edx();
|
|
#ifdef ENABLE_386_DYNAREC_LOG
|
|
x386_dynarec_log("Triple fault - reset\n");
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
if (in_smm && smi_line && is_pentium)
|
|
{
|
|
enter_smm();
|
|
}
|
|
|
|
else if (trap)
|
|
{
|
|
trap = 0;
|
|
flags_rebuild();
|
|
if (msw&1)
|
|
{
|
|
pmodeint(1,0);
|
|
}
|
|
else
|
|
{
|
|
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
|
|
writememw(ss,(SP-4)&0xFFFF,CS);
|
|
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
|
|
SP-=6;
|
|
addr = (1 << 2) + idt.base;
|
|
cpu_state.flags &= ~I_FLAG;
|
|
cpu_state.flags &= ~T_FLAG;
|
|
cpu_state.pc=readmemw(0,addr);
|
|
loadcs(readmemw(0,addr+2));
|
|
}
|
|
}
|
|
else if (nmi && nmi_enable && nmi_mask)
|
|
{
|
|
cpu_state.oldpc = cpu_state.pc;
|
|
x86_int(2);
|
|
nmi_enable = 0;
|
|
if (nmi_auto_clear)
|
|
{
|
|
nmi_auto_clear = 0;
|
|
nmi = 0;
|
|
}
|
|
}
|
|
else if ((cpu_state.flags & I_FLAG) && pic_intpending)
|
|
{
|
|
vector = picinterrupt();
|
|
if (vector != -1)
|
|
{
|
|
CPU_BLOCK_END();
|
|
flags_rebuild();
|
|
if (msw&1)
|
|
{
|
|
pmodeint(vector,0);
|
|
}
|
|
else
|
|
{
|
|
writememw(ss,(SP-2)&0xFFFF,cpu_state.flags);
|
|
writememw(ss,(SP-4)&0xFFFF,CS);
|
|
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
|
|
SP-=6;
|
|
addr=vector<<2;
|
|
cpu_state.flags &= ~I_FLAG;
|
|
cpu_state.flags &= ~T_FLAG;
|
|
cpu_state.pc=readmemw(0,addr);
|
|
loadcs(readmemw(0,addr+2));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t)tsc))
|
|
timer_process();
|
|
cycles_main -= (cycles_start - cycles);
|
|
}
|
|
}
|
|
#endif
|