f6ef1f833c
Thoroughly clean up the code to vastly reduce the number of compiler warnings and found and fixed several bugs in the process; Applied all mainline PCem commits; Added SCSI hard disk emulation; Commented out all unfinished machines and graphics cards; Added the AOpen AP53 and ASUS P/I-P55T2 machines as well as another Tyan 440FX machine, all three with AMI WinBIOS (patch from TheCollector1995); Added the Diamond Stealth 3D 3000 (S3 ViRGE/VX) graphics card (patch from TheCollector1995); Added the PS/2 XT IDE (AccuLogic) HDD Controller (patch from TheCollector1995); Added Microsoft/Logitech Bus Mouse emulation (patch from waltje); Overhauled the makefiles (patch from waltje); Added the Adaptec AHA-1542CF SCSI controller (patch from waltje); Added preliminary (but still unfinished) Adaptec AHA-154x SCSI controller BIOS support (patch from waltje); Added an ISABugger debugging device (patch from waltje); Added sanity checks to the Direct3D code.
307 lines
9.4 KiB
C
307 lines
9.4 KiB
C
/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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#include "ps1.h"
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#include "rom.h"
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#include "lpt.h"
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#include "serial.h"
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static rom_t ps1_high_rom;
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static uint8_t ps1_92, ps1_94, ps1_102, ps1_103, ps1_104, ps1_105, ps1_190;
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static int ps1_e0_addr;
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static uint8_t ps1_e0_regs[256];
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static struct
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{
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uint8_t status, int_status;
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uint8_t attention, ctrl;
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} ps1_hd;
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uint8_t ps1_read(uint16_t port, void *p)
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{
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uint8_t temp;
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switch (port)
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{
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case 0x91:
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return 0;
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case 0x92:
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return ps1_92;
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case 0x94:
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return ps1_94;
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case 0x102:
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return ps1_102 | 8;
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case 0x103:
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return ps1_103;
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case 0x104:
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return ps1_104;
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case 0x105:
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return ps1_105;
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case 0x190:
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return ps1_190;
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case 0x322:
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temp = ps1_hd.status;
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break;
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case 0x324:
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temp = ps1_hd.int_status;
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ps1_hd.int_status &= ~0x02;
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break;
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default:
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temp = 0xff;
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break;
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}
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return temp;
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}
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void ps1_write(uint16_t port, uint8_t val, void *p)
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{
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switch (port)
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{
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case 0x0092:
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ps1_92 = val;
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mem_a20_alt = val & 2;
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mem_a20_recalc();
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break;
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case 0x94:
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ps1_94 = val;
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break;
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case 0x102:
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lpt1_remove();
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if (val & 0x04)
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serial1_init(0x3f8, 4);
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else
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serial1_remove();
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if (val & 0x10)
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{
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switch ((val >> 5) & 3)
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{
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case 0:
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lpt1_init(0x3bc);
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break;
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case 1:
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lpt1_init(0x378);
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break;
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case 2:
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lpt1_init(0x278);
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break;
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}
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}
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ps1_102 = val;
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break;
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case 0x103:
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ps1_103 = val;
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break;
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case 0x104:
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ps1_104 = val;
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break;
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case 0x105:
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ps1_105 = val;
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break;
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case 0x190:
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ps1_190 = val;
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break;
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case 0x322:
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ps1_hd.ctrl = val;
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if (val & 0x80)
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ps1_hd.status |= 0x02;
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break;
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case 0x324:
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ps1_hd.attention = val & 0xf0;
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if (ps1_hd.attention)
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ps1_hd.status = 0x14;
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break;
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}
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}
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void ps1mb_init()
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{
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io_sethandler(0x0091, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0092, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0094, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0102, 0x0004, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0190, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0320, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0322, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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io_sethandler(0x0324, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
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if (!enable_xtide)
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{
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rom_init(&ps1_high_rom,
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"roms/ibmps1es/f80000_shell.bin",
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0xf80000,
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0x80000,
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0x7ffff,
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0,
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MEM_MAPPING_EXTERNAL);
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}
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/* rom_init_interleaved(&ps1_high_rom,
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"roms/ibmps1es/ibm_1057757_24-05-90.bin",
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"roms/ibmps1es/ibm_1057757_29-15-90.bin",
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0xfc0000,
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0x40000,
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0x3ffff,
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0,
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MEM_MAPPING_EXTERNAL);*/
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ps1_190 = 0;
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lpt1_remove();
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lpt2_remove();
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lpt1_init(0x3bc);
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serial1_remove();
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serial2_remove();
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memset(&ps1_hd, 0, sizeof(ps1_hd));
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}
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/*PS/1 Model 2121.
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This is similar to the model 2011 but some of the functionality has moved to a
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chip at ports 0xe0 (index)/0xe1 (data). The only functions I have identified
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are enables for the first 512kb and next 128kb of RAM, in bits 0 of registers
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0 and 1 respectively.
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Port 0x105 has bit 7 forced high. Without this 128kb of memory will be missed
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by the BIOS on cold boots.
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The reserved 384kb is remapped to the top of extended memory. If this is not
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done then you get an error on startup.
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*/
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static uint8_t ps1_m2121_read(uint16_t port, void *p)
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{
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uint8_t temp;
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switch (port)
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{
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case 0x91:
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return 0;
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case 0x92:
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return ps1_92;
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case 0x94:
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return ps1_94;
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case 0xe1:
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return ps1_e0_regs[ps1_e0_addr];
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case 0x102:
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return ps1_102;
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case 0x103:
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return ps1_103;
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case 0x104:
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return ps1_104;
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case 0x105:
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return ps1_105 | 0x80;
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case 0x190:
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return ps1_190;
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default:
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temp = 0xff;
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break;
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}
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return temp;
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}
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static void ps1_m2121_recalc_memory()
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{
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/*Enable first 512kb*/
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mem_set_mem_state(0x00000, 0x80000, (ps1_e0_regs[0] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
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/*Enable 512-640kb*/
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mem_set_mem_state(0x80000, 0x20000, (ps1_e0_regs[1] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
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}
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void ps1_m2121_write(uint16_t port, uint8_t val, void *p)
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{
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switch (port)
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{
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case 0x0092:
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if (val & 1)
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{
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softresetx86();
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cpu_set_edx();
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}
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ps1_92 = val & ~1;
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mem_a20_alt = val & 2;
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mem_a20_recalc();
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break;
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case 0x94:
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ps1_94 = val;
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break;
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case 0xe0:
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ps1_e0_addr = val;
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break;
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case 0xe1:
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ps1_e0_regs[ps1_e0_addr] = val;
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ps1_m2121_recalc_memory();
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break;
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case 0x102:
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lpt1_remove();
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if (val & 0x04)
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serial1_init(0x3f8, 4);
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else
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serial1_remove();
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if (val & 0x10)
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{
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switch ((val >> 5) & 3)
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{
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case 0:
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lpt1_init(0x3bc);
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break;
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case 1:
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lpt1_init(0x378);
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break;
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case 2:
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lpt1_init(0x278);
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break;
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}
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}
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ps1_102 = val;
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break;
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case 0x103:
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ps1_103 = val;
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break;
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case 0x104:
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ps1_104 = val;
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break;
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case 0x105:
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ps1_105 = val;
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break;
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case 0x190:
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ps1_190 = val;
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break;
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}
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}
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void ps1mb_m2121_init()
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{
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io_sethandler(0x0091, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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io_sethandler(0x0092, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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io_sethandler(0x0094, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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io_sethandler(0x00e0, 0x0002, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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io_sethandler(0x0102, 0x0004, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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io_sethandler(0x0190, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
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rom_init(&ps1_high_rom,
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"roms/ibmps1_2121/fc0000_shell.bin",
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0xfc0000,
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0x40000,
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0x3ffff,
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0,
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MEM_MAPPING_EXTERNAL);
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ps1_190 = 0;
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lpt1_remove();
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lpt2_remove();
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lpt1_init(0x3bc);
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serial1_remove();
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serial2_remove();
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mem_remap_top_384k();
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}
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