608 lines
21 KiB
C
608 lines
21 KiB
C
static uint32_t
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fpu_save_environment(void)
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{
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int tag;
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unsigned offset = 0;
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/* read all registers in stack order and update x87 tag word */
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for (int n = 0; n < 8; n++) {
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// update tag only if it is not empty
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if (!IS_TAG_EMPTY(n)) {
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tag = FPU_tagof(FPU_read_regi(n));
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FPU_settagi(tag, n);
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}
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}
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fpu_state.swd = (fpu_state.swd & ~(7 << 11)) | ((fpu_state.tos & 7) << 11);
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switch ((cr0 & 1) | (cpu_state.op32 & 0x100)) {
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case 0x000:
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{ /*16-bit real mode*/
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uint16_t tmp;
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uint32_t fp_ip;
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uint32_t fp_dp;
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fp_ip = ((uint32_t) (fpu_state.fcs << 4)) | fpu_state.fip;
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fp_dp = ((uint32_t) (fpu_state.fds << 4)) | fpu_state.fdp;
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tmp = i387_get_control_word();
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writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
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tmp = i387_get_status_word();
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writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
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tmp = fpu_state.tag;
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writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
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tmp = fp_ip & 0xffff;
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writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
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tmp = (uint16_t) ((fp_ip & 0xf0000) >> 4) | fpu_state.foo;
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writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
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tmp = fp_dp & 0xffff;
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writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
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tmp = (uint16_t) ((fp_dp & 0xf0000) >> 4);
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writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
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offset = 0x0e;
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}
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break;
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case 0x001:
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{ /*16-bit protected mode*/
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uint16_t tmp;
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tmp = i387_get_control_word();
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writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
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tmp = i387_get_status_word();
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writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
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tmp = fpu_state.tag;
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writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
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tmp = (uint16_t) (fpu_state.fip) & 0xffff;
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writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
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tmp = fpu_state.fcs;
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writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
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tmp = (uint16_t) (fpu_state.fdp) & 0xffff;
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writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
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tmp = fpu_state.fds;
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writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
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offset = 0x0e;
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}
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break;
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case 0x100:
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{ /*32-bit real mode*/
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uint32_t tmp;
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uint32_t fp_ip;
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uint32_t fp_dp;
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fp_ip = ((uint32_t) (fpu_state.fcs << 4)) | fpu_state.fip;
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fp_dp = ((uint32_t) (fpu_state.fds << 4)) | fpu_state.fdp;
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tmp = 0xffff0000 | i387_get_control_word();
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writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
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tmp = 0xffff0000 | i387_get_status_word();
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writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
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tmp = 0xffff0000 | fpu_state.tag;
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writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
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tmp = 0xffff0000 | (fp_ip & 0xffff);
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writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
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tmp = ((fp_ip & 0xffff0000) >> 4) | fpu_state.foo;
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writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
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tmp = 0xffff0000 | (fp_dp & 0xffff);
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writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
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tmp = (fp_dp & 0xffff0000) >> 4;
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writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
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offset = 0x1c;
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}
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break;
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case 0x101:
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{ /*32-bit protected mode*/
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uint32_t tmp;
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tmp = 0xffff0000 | i387_get_control_word();
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writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
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tmp = 0xffff0000 | i387_get_status_word();
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writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
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tmp = 0xffff0000 | fpu_state.tag;
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writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
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tmp = (uint32_t) (fpu_state.fip);
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writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
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tmp = fpu_state.fcs | (((uint32_t) (fpu_state.foo)) << 16);
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writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
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tmp = (uint32_t) (fpu_state.fdp);
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writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
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tmp = 0xffff0000 | fpu_state.fds;
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writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
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offset = 0x1c;
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}
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break;
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}
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return (cpu_state.eaaddr + offset);
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}
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static uint32_t
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fpu_load_environment(void)
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{
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unsigned offset = 0;
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switch ((cr0 & 1) | (cpu_state.op32 & 0x100)) {
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case 0x000:
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{ /*16-bit real mode*/
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uint16_t tmp;
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uint32_t fp_ip;
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uint32_t fp_dp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
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fp_dp = (tmp & 0xf000) << 4;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
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fpu_state.fdp = fp_dp | tmp;
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fpu_state.fds = 0;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
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fp_ip = (tmp & 0xf000) << 4;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
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fpu_state.fip = fp_ip | tmp;
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fpu_state.fcs = 0;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
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fpu_state.tag = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
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fpu_state.swd = tmp;
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fpu_state.tos = (tmp >> 11) & 7;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
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fpu_state.cwd = tmp;
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offset = 0x0e;
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}
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break;
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case 0x001:
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{ /*16-bit protected mode*/
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uint16_t tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
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fpu_state.fds = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
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fpu_state.fdp = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
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fpu_state.fcs = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
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fpu_state.fip = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
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fpu_state.tag = tmp;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
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fpu_state.swd = tmp;
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fpu_state.tos = (tmp >> 11) & 7;
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tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
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fpu_state.cwd = tmp;
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offset = 0x0e;
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}
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break;
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case 0x100:
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{ /*32-bit real mode*/
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uint32_t tmp;
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uint32_t fp_ip;
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uint32_t fp_dp;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
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fp_dp = (tmp & 0x0ffff000) << 4;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
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fp_dp |= (tmp & 0xffff);
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fpu_state.fdp = fp_dp;
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fpu_state.fds = 0;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
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fpu_state.foo = tmp & 0x07ff;
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fp_ip = (tmp & 0x0ffff000) << 4;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
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fp_ip |= (tmp & 0xffff);
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fpu_state.fip = fp_ip;
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fpu_state.fcs = 0;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
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fpu_state.tag = tmp & 0xffff;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
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fpu_state.swd = tmp & 0xffff;
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fpu_state.tos = (tmp >> 11) & 7;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
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fpu_state.cwd = tmp & 0xffff;
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offset = 0x1c;
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}
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break;
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case 0x101:
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{ /*32-bit protected mode*/
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uint32_t tmp;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
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fpu_state.fds = tmp & 0xffff;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
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fpu_state.fdp = tmp;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
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fpu_state.fcs = tmp & 0xffff;
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fpu_state.foo = (tmp >> 16) & 0x07ff;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
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fpu_state.fip = tmp;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
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fpu_state.tag = tmp & 0xffff;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
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fpu_state.swd = tmp & 0xffff;
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fpu_state.tos = (tmp >> 11) & 7;
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tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
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fpu_state.cwd = tmp & 0xffff;
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offset = 0x1c;
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}
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break;
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}
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/* always set bit 6 as '1 */
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fpu_state.cwd = (fpu_state.cwd & ~FPU_CW_Reserved_Bits) | 0x0040;
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/* check for unmasked exceptions */
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if (fpu_state.swd & ~fpu_state.cwd & FPU_CW_Exceptions_Mask) {
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/* set the B and ES bits in the status-word */
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fpu_state.swd |= (FPU_SW_Summary | FPU_SW_Backward);
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} else {
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/* clear the B and ES bits in the status-word */
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fpu_state.swd &= ~(FPU_SW_Summary | FPU_SW_Backward);
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}
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return (cpu_state.eaaddr + offset);
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}
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static int
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sf_FLDCW_a16(uint32_t fetchdat)
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{
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uint16_t tempw;
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FP_ENTER();
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fetch_ea_16(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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tempw = geteaw();
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if (cpu_state.abrt)
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return 1;
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fpu_state.cwd = (tempw & ~FPU_CW_Reserved_Bits) | 0x0040; // bit 6 is reserved as '1
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/* check for unmasked exceptions */
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if (fpu_state.swd & (~fpu_state.cwd & FPU_CW_Exceptions_Mask)) {
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/* set the B and ES bits in the status-word */
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fpu_state.swd |= (FPU_SW_Summary | FPU_SW_Backward);
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} else {
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/* clear the B and ES bits in the status-word */
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fpu_state.swd &= ~(FPU_SW_Summary | FPU_SW_Backward);
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}
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldcw) : (x87_concurrency.fldcw * cpu_multi));
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return 0;
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}
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#ifndef FPU_8087
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static int
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sf_FLDCW_a32(uint32_t fetchdat)
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{
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uint16_t tempw;
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FP_ENTER();
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fetch_ea_32(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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tempw = geteaw();
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if (cpu_state.abrt)
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return 1;
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fpu_state.cwd = (tempw & ~FPU_CW_Reserved_Bits) | 0x0040; // bit 6 is reserved as '1
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/* check for unmasked exceptions */
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if (fpu_state.swd & (~fpu_state.cwd & FPU_CW_Exceptions_Mask)) {
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/* set the B and ES bits in the status-word */
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fpu_state.swd |= (FPU_SW_Summary | FPU_SW_Backward);
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} else {
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/* clear the B and ES bits in the status-word */
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fpu_state.swd &= ~(FPU_SW_Summary | FPU_SW_Backward);
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}
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldcw) : (x87_timings.fldcw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldcw) : (x87_concurrency.fldcw * cpu_multi));
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return 0;
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}
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#endif
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static int
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sf_FNSTCW_a16(uint32_t fetchdat)
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{
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uint16_t cwd = i387_get_control_word();
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FP_ENTER();
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(cwd);
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
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return cpu_state.abrt;
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}
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#ifndef FPU_8087
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static int
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sf_FNSTCW_a32(uint32_t fetchdat)
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{
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uint16_t cwd = i387_get_control_word();
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FP_ENTER();
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(cwd);
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
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return cpu_state.abrt;
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}
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#endif
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static int
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sf_FNSTSW_a16(uint32_t fetchdat)
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{
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uint16_t swd = i387_get_status_word();
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FP_ENTER();
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(swd);
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
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return cpu_state.abrt;
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}
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#ifndef FPU_8087
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static int
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sf_FNSTSW_a32(uint32_t fetchdat)
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{
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uint16_t swd = i387_get_status_word();
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FP_ENTER();
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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seteaw(swd);
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
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return cpu_state.abrt;
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}
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#endif
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#ifdef FPU_8087
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static int
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sf_FI(uint32_t fetchdat)
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{
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FP_ENTER();
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cpu_state.pc++;
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fpu_state.cwd &= ~FPU_SW_Summary;
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if (rmdat == 0xe1)
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fpu_state.cwd |= FPU_SW_Summary;
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wait(3, 0);
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return 0;
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}
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#else
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static int
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sf_FNSTSW_AX(uint32_t fetchdat)
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{
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FP_ENTER();
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cpu_state.pc++;
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AX = i387_get_status_word();
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstcw_sw) : (x87_timings.fstcw_sw * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstcw_sw) : (x87_concurrency.fstcw_sw * cpu_multi));
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return 0;
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}
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#endif
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static int
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sf_FRSTOR_a16(uint32_t fetchdat)
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{
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floatx80 tmp;
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int offset;
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FP_ENTER();
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fetch_ea_16(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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offset = fpu_load_environment();
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for (int n = 0; n < 8; n++) {
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tmp.fraction = readmemq(easeg, offset + (n * 10));
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tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
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FPU_save_regi_tag(tmp, IS_TAG_EMPTY(n) ? X87_TAG_EMPTY : FPU_tagof(tmp), n);
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}
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CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
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CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.frstor) : (x87_concurrency.frstor * cpu_multi));
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return cpu_state.abrt;
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}
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#ifndef FPU_8087
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static int
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sf_FRSTOR_a32(uint32_t fetchdat)
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{
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floatx80 tmp;
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int offset;
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FP_ENTER();
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fetch_ea_32(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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offset = fpu_load_environment();
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for (int n = 0; n < 8; n++) {
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tmp.fraction = readmemq(easeg, offset + (n * 10));
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tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
|
|
FPU_save_regi_tag(tmp, IS_TAG_EMPTY(n) ? X87_TAG_EMPTY : FPU_tagof(tmp), n);
|
|
}
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.frstor) : (x87_concurrency.frstor * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
sf_FNSAVE_a16(uint32_t fetchdat)
|
|
{
|
|
floatx80 stn;
|
|
int offset;
|
|
|
|
FP_ENTER();
|
|
fetch_ea_16(fetchdat);
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
offset = fpu_save_environment();
|
|
/* save all registers in stack order. */
|
|
for (int m = 0; m < 8; m++) {
|
|
stn = FPU_read_regi(m);
|
|
writememq(easeg, offset + (m * 10), stn.fraction);
|
|
writememw(easeg, offset + (m * 10) + 8, stn.exp);
|
|
}
|
|
|
|
#ifdef FPU_8087
|
|
fpu_state.swd = 0x3FF;
|
|
#else
|
|
fpu_state.cwd = 0x37F;
|
|
#endif
|
|
fpu_state.swd = 0;
|
|
fpu_state.tos = 0;
|
|
fpu_state.tag = 0xffff;
|
|
cpu_state.ismmx = 0;
|
|
fpu_state.foo = 0;
|
|
fpu_state.fds = 0;
|
|
fpu_state.fdp = 0;
|
|
fpu_state.fcs = 0;
|
|
fpu_state.fip = 0;
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsave) : (x87_concurrency.fsave * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#ifndef FPU_8087
|
|
static int
|
|
sf_FNSAVE_a32(uint32_t fetchdat)
|
|
{
|
|
floatx80 stn;
|
|
int offset;
|
|
|
|
FP_ENTER();
|
|
fetch_ea_32(fetchdat);
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
offset = fpu_save_environment();
|
|
/* save all registers in stack order. */
|
|
for (int m = 0; m < 8; m++) {
|
|
stn = FPU_read_regi(m);
|
|
writememq(easeg, offset + (m * 10), stn.fraction);
|
|
writememw(easeg, offset + (m * 10) + 8, stn.exp);
|
|
}
|
|
|
|
# ifdef FPU_8087
|
|
fpu_state.swd = 0x3FF;
|
|
# else
|
|
fpu_state.cwd = 0x37F;
|
|
# endif
|
|
fpu_state.swd = 0;
|
|
fpu_state.tos = 0;
|
|
fpu_state.tag = 0xffff;
|
|
cpu_state.ismmx = 0;
|
|
fpu_state.foo = 0;
|
|
fpu_state.fds = 0;
|
|
fpu_state.fdp = 0;
|
|
fpu_state.fcs = 0;
|
|
fpu_state.fip = 0;
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsave) : (x87_concurrency.fsave * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
sf_FNCLEX(uint32_t fetchdat)
|
|
{
|
|
FP_ENTER();
|
|
cpu_state.pc++;
|
|
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary | FPU_SW_Stack_Fault | FPU_SW_Precision | FPU_SW_Underflow | FPU_SW_Overflow | FPU_SW_Zero_Div | FPU_SW_Denormal_Op | FPU_SW_Invalid);
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fnop) : (x87_concurrency.fnop * cpu_multi));
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sf_FNINIT(uint32_t fetchdat)
|
|
{
|
|
FP_ENTER();
|
|
cpu_state.pc++;
|
|
#ifdef FPU_8087
|
|
fpu_state.cwd = 0x3FF;
|
|
#else
|
|
fpu_state.cwd = 0x37F;
|
|
#endif
|
|
fpu_state.swd = 0;
|
|
fpu_state.tos = 0;
|
|
fpu_state.tag = 0xffff;
|
|
fpu_state.foo = 0;
|
|
fpu_state.fds = 0;
|
|
fpu_state.fdp = 0;
|
|
fpu_state.fcs = 0;
|
|
fpu_state.fip = 0;
|
|
cpu_state.ismmx = 0;
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.finit) : (x87_timings.finit * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.finit) : (x87_concurrency.finit * cpu_multi));
|
|
CPU_BLOCK_END();
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sf_FLDENV_a16(uint32_t fetchdat)
|
|
{
|
|
int tag;
|
|
|
|
FP_ENTER();
|
|
fetch_ea_16(fetchdat);
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
fpu_load_environment();
|
|
/* read all registers in stack order and update x87 tag word */
|
|
for (int n = 0; n < 8; n++) {
|
|
// update tag only if it is not empty
|
|
if (!IS_TAG_EMPTY(n)) {
|
|
tag = FPU_tagof(FPU_read_regi(n));
|
|
FPU_settagi(tag, n);
|
|
}
|
|
}
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldenv) : (x87_timings.fldenv * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldenv) : (x87_concurrency.fldenv * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#ifndef FPU_8087
|
|
static int
|
|
sf_FLDENV_a32(uint32_t fetchdat)
|
|
{
|
|
int tag;
|
|
|
|
FP_ENTER();
|
|
fetch_ea_32(fetchdat);
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
fpu_load_environment();
|
|
/* read all registers in stack order and update x87 tag word */
|
|
for (int n = 0; n < 8; n++) {
|
|
// update tag only if it is not empty
|
|
if (!IS_TAG_EMPTY(n)) {
|
|
tag = FPU_tagof(FPU_read_regi(n));
|
|
FPU_settagi(tag, n);
|
|
}
|
|
}
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fldenv) : (x87_timings.fldenv * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fldenv) : (x87_concurrency.fldenv * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
sf_FNSTENV_a16(uint32_t fetchdat)
|
|
{
|
|
FP_ENTER();
|
|
fetch_ea_16(fetchdat);
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
fpu_save_environment();
|
|
/* mask all floating point exceptions */
|
|
fpu_state.cwd |= FPU_CW_Exceptions_Mask;
|
|
/* clear the B and ES bits in the status word */
|
|
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary);
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#ifndef FPU_8087
|
|
static int
|
|
sf_FNSTENV_a32(uint32_t fetchdat)
|
|
{
|
|
FP_ENTER();
|
|
fetch_ea_32(fetchdat);
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
fpu_save_environment();
|
|
/* mask all floating point exceptions */
|
|
fpu_state.cwd |= FPU_CW_Exceptions_Mask;
|
|
/* clear the B and ES bits in the status word */
|
|
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary);
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
|
|
return cpu_state.abrt;
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
sf_FNOP(uint32_t fetchdat)
|
|
{
|
|
FP_ENTER();
|
|
cpu_state.pc++;
|
|
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
|
|
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fnop) : (x87_concurrency.fnop * cpu_multi));
|
|
return 0;
|
|
}
|