562 lines
16 KiB
C
562 lines
16 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the Winbond W83781D hardware monitoring chip.
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*
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*
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*
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* Author: RichardG, <richardg867@gmail.com>
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* Copyright 2020 RichardG.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#define HAVE_STDARG_H
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/smbus.h>
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#include <86box/hwm.h>
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#define W83781D_SMBUS 0x10000
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#define W83781D_AS99127F_REV1 0x20000
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#define W83781D_AS99127F_REV2 0x40000
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#define W83781D_AS99127F 0x60000 /* special mask covering both _REV1 and _REV2 */
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#define W83781D_VENDOR_ID ((dev->local & W83781D_AS99127F_REV1) ? 0x12C3 : 0x5CA3)
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#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
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#define W83781D_RPM_TO_REG(r, d) CLAMP(1350000 / (r * d), 1, 255)
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#define W83781D_TEMP_TO_REG(t) ((t) << 8)
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#define W83781D_VOLTAGE_TO_REG(v) ((v) >> 4)
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typedef struct {
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uint32_t local;
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hwm_values_t* values;
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uint8_t regs[256];
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uint8_t regs_bank1[7];
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uint8_t regs_bank2[7];
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uint8_t addr_register;
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uint8_t data_register;
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uint8_t smbus_addr_main;
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uint8_t smbus_addr_temp2;
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uint8_t smbus_addr_temp3;
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uint8_t hbacs;
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uint8_t active_bank;
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} w83781d_t;
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static uint8_t w83781d_isa_read(uint16_t port, void *priv);
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static uint8_t w83781d_smbus_read_byte(uint8_t addr, void *priv);
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static uint8_t w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv);
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static uint16_t w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv);
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static uint8_t w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank);
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static void w83781d_isa_write(uint16_t port, uint8_t val, void *priv);
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static void w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv);
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static void w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv);
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static void w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv);
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static uint8_t w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank);
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static void w83781d_reset(w83781d_t *dev, uint8_t initialization);
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#ifdef ENABLE_W83781D_LOG
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int w83781d_do_log = ENABLE_W83781D_LOG;
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static void
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w83781d_log(const char *fmt, ...)
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{
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va_list ap;
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if (w83781d_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define w83781d_log(fmt, ...)
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#endif
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static void
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w83781d_remap(w83781d_t *dev)
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{
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if (!(dev->local & W83781D_SMBUS)) return;
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smbus_removehandler(0x00, 0x80,
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w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
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w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
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dev);
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if (dev->smbus_addr_main) smbus_sethandler(dev->smbus_addr_main, 1,
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w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
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w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
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dev);
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if (dev->smbus_addr_temp2) smbus_sethandler(dev->smbus_addr_temp2, 1,
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w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
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w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
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dev);
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if (dev->smbus_addr_temp3) smbus_sethandler(dev->smbus_addr_temp3, 1,
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w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
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w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
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dev);
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}
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static uint8_t
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w83781d_isa_read(uint16_t port, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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uint8_t ret = 0xFF;
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switch (port - (dev->local & 0xFFFF)) {
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case 0x0:
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ret = dev->addr_register & 0x7F;
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break;
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case 0x1:
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ret = w83781d_read(dev, dev->addr_register, dev->active_bank);
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if (dev->active_bank == 0 &&
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(dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
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(dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
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/* auto-increment registers */
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dev->addr_register++;
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}
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break;
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}
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return ret;
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}
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static uint8_t
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w83781d_smbus_read_byte(uint8_t addr, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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return w83781d_read(dev, dev->addr_register, 0);
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}
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static uint8_t
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w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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return w83781d_read(dev, cmd, 0);
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}
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static uint16_t
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w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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uint8_t rethi = 0;
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uint8_t retlo = 0;
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uint8_t bank = 0;
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if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
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if (addr == dev->smbus_addr_temp2)
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bank = 2;
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else
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bank = 3;
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switch (cmd & 0x3) {
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case 0x0: /* temperature */
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rethi = w83781d_read(dev, 0x50, bank);
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retlo = w83781d_read(dev, 0x51, bank);
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break;
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case 0x1: /* configuration */
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rethi = retlo = w83781d_read(dev, 0x52, bank);
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break;
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case 0x2: /* Thyst */
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rethi = w83781d_read(dev, 0x53, bank);
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retlo = w83781d_read(dev, 0x54, bank);
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break;
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case 0x3: /* Tos */
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rethi = w83781d_read(dev, 0x55, bank);
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retlo = w83781d_read(dev, 0x56, bank);
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break;
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}
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} else {
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rethi = retlo = w83781d_read(dev, cmd, bank);
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}
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return (retlo << 8) | rethi; /* byte-swapped for some reason */
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}
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static uint8_t
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w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank)
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{
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uint8_t ret = 0;
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if ((reg >> 4) == 0x5 && bank != 0) {
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/* bank-switched temperature registers */
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if (bank == 1)
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ret = dev->regs_bank1[reg - 0x50];
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else
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ret = dev->regs_bank2[reg - 0x50];
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} else {
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/* regular registers */
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if (reg == 0x4F) /* special case for two-byte vendor ID register */
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ret = dev->hbacs ? (W83781D_VENDOR_ID >> 8) : (W83781D_VENDOR_ID & 0xFF);
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else if (reg >= 0x60 && reg <= 0x7F) /* read auto-increment value RAM registers from their non-auto-increment locations */
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ret = dev->regs[reg - 0x40];
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else if (reg >= 0x80 && reg <= 0x92) /* AS99127F mirrors 00-12 to 80-92 */
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ret = dev->regs[reg - 0x80];
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else
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ret = dev->regs[reg];
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}
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w83781d_log("w83781d_read(%02x, %d) = %02x\n", reg, bank, ret);
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return ret;
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}
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static void
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w83781d_isa_write(uint16_t port, uint8_t val, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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switch (port - (dev->local & 0xFFFF)) {
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case 0x0:
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dev->addr_register = val & 0x7F;
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break;
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case 0x1:
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w83781d_write(dev, dev->addr_register, val, dev->active_bank);
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if (dev->active_bank == 0 &&
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(dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
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(dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
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/* auto-increment registers */
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dev->addr_register++;
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}
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break;
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}
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}
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static void
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w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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dev->addr_register = val;
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}
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static void
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w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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w83781d_write(dev, cmd, val, 0);
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}
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static void
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w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv)
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{
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w83781d_t *dev = (w83781d_t *) priv;
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uint8_t valhi = (val >> 8);
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uint8_t vallo = (val & 0xFF);
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uint8_t bank = 0;
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if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
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if (addr == dev->smbus_addr_temp2)
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bank = 2;
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else
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bank = 3;
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switch (cmd & 0x3) {
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case 0x0: /* temperature */
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w83781d_write(dev, 0x50, valhi, bank);
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w83781d_write(dev, 0x51, vallo, bank);
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break;
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case 0x1: /* configuration */
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w83781d_write(dev, 0x52, vallo, bank);
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break;
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case 0x2: /* Thyst */
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w83781d_write(dev, 0x53, valhi, bank);
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w83781d_write(dev, 0x54, vallo, bank);
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break;
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case 0x3: /* Tos */
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w83781d_write(dev, 0x55, valhi, bank);
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w83781d_write(dev, 0x56, vallo, bank);
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break;
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break;
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}
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return;
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}
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w83781d_write(dev, cmd, vallo, bank);
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}
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static uint8_t
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w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
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{
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uint8_t remap = 0;
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if ((reg >> 4) == 0x5 && bank != 0) {
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/* bank-switched temperature registers */
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switch (reg) {
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case 0x50: case 0x51:
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/* read-only registers */
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return 0;
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}
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if (bank == 1)
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dev->regs_bank1[reg - 0x50] = val;
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else
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dev->regs_bank2[reg - 0x50] = val;
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return 1;
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}
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/* regular registers */
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switch (reg) {
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case 0x41: case 0x42: case 0x4F: case 0x58:
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case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2A:
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case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6A:
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/* read-only registers */
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return 0;
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}
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if (reg >= 0x60 && reg <= 0x7F) /* write auto-increment value RAM registers to their non-auto-increment locations */
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dev->regs[reg - 0x40] = val;
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else if (reg >= 0x80 && reg <= 0x92) /* AS99127F mirrors 00-12 to 80-92 */
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dev->regs[reg - 0x80] = val;
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else
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dev->regs[reg] = val;
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switch (reg) {
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case 0x40:
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if (val >> 7) {
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/* INITIALIZATION bit resets all registers except main SMBus address */
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w83781d_reset(dev, 1);
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}
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break;
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case 0x47:
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/* update FAN1/FAN2 values to match the new divisor */
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dev->regs[0x28] = W83781D_RPM_TO_REG(dev->values->fans[0], 1 << ((dev->regs[0x47] >> 4) & 0x3));
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dev->regs[0x29] = W83781D_RPM_TO_REG(dev->values->fans[1], 1 << ((dev->regs[0x47] >> 6) & 0x3));
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break;
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case 0x48:
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/* set main SMBus address */
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if (dev->local & W83781D_SMBUS) {
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dev->smbus_addr_main = (dev->regs[0x48] & 0x7F);
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remap = 1;
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}
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break;
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case 0x4A:
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/* set TEMP2 and TEMP3 SMBus addresses */
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if (dev->local & W83781D_SMBUS) {
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/* DIS_T2 and DIS_T3 bits disable those interfaces */
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if ((dev->regs[0x4A] >> 3) & 0x1)
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dev->smbus_addr_temp2 = 0x00;
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else
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dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x4A] & 0x7);
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if (dev->regs[0x4A] >> 7)
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dev->smbus_addr_temp3 = 0x00;
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else
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dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x4A] >> 4) & 0x7);
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remap = 1;
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}
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break;
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case 0x4B:
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/* update FAN3 value to match the new divisor */
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dev->regs[0x2A] = W83781D_RPM_TO_REG(dev->values->fans[2], 1 << ((dev->regs[0x4B] >> 6) & 0x3));
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break;
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case 0x4E:
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dev->hbacs = (dev->regs[0x4E] & 0x80);
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/* FIXME: Winbond's datasheet does not specify how BANKSEL[0:2] work */
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if (dev->regs[0x4E] & 0x1)
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dev->active_bank = 0;
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else if (dev->regs[0x4E] & 0x2)
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dev->active_bank = 1;
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else if (dev->regs[0x4E] & 0x4)
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dev->active_bank = 2;
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break;
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}
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if (remap)
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w83781d_remap(dev);
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return 1;
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}
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static void
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w83781d_reset(w83781d_t *dev, uint8_t initialization)
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{
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memset(dev->regs, 0, 256);
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memset(dev->regs + 0xC0, 0xFF, 32); /* C0-DF are 0xFF at least on the AS99127F */
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memset(dev->regs_bank1, 0, 6);
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memset(dev->regs_bank2, 0, 6);
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uint8_t i;
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for (i = 0; i <= 6; i++)
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dev->regs[0x20 + i] = W83781D_VOLTAGE_TO_REG(dev->values->voltages[i]);
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dev->regs[0x27] = dev->values->temperatures[0];
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for (i = 0; i <= 2; i++)
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dev->regs[0x28 + i] = W83781D_RPM_TO_REG(dev->values->fans[i], 2);
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dev->regs[0x40] = 0x01;
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dev->regs[0x46] = 0x40;
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dev->regs[0x47] = 0x50;
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if (dev->local & W83781D_SMBUS) {
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if (!initialization) /* don't reset main SMBus address if the reset was triggered by the INITIALIZATION bit */
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dev->smbus_addr_main = 0x2D;
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dev->regs[0x48] = dev->smbus_addr_main;
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dev->regs[0x4A] = 0x01;
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dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x4A] & 0x7);
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dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x4A] >> 4) & 0x7);
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} else {
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dev->regs[0x48] = 0x00;
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dev->regs[0x4A] = 0x88;
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dev->smbus_addr_temp2 = dev->smbus_addr_temp3 = 0x00;
|
|
}
|
|
dev->regs[0x49] = 0x02;
|
|
dev->regs[0x4B] = 0x44;
|
|
dev->regs[0x4C] = 0x01;
|
|
dev->regs[0x4D] = 0x15;
|
|
dev->regs[0x4E] = 0x80;
|
|
dev->hbacs = (dev->regs[0x4E] & 0x80);
|
|
dev->regs[0x4F] = W83781D_VENDOR_ID >> 8;
|
|
dev->regs[0x57] = 0x80;
|
|
dev->regs[0x58] = (dev->local & W83781D_AS99127F) ? 0x31 : 0x10;
|
|
|
|
/*
|
|
* Initialize proprietary registers on the AS99127F. The BIOS accesses some
|
|
* of these on boot through read_byte_cmd on the TEMP2 address, hanging on
|
|
* POST code C1 if they're set to 0. There's no documentation on what these
|
|
* are for. The following values were dumped from a live, initialized
|
|
* AS99127F Rev. 2 on a P4B motherboard, and they seem to work well enough.
|
|
*/
|
|
if (dev->local & W83781D_AS99127F) {
|
|
/* 0x00 appears to mirror IN2 Low Limit */
|
|
dev->regs[0x01] = dev->regs[0x23]; /* appears to mirror IN3 */
|
|
dev->regs[0x02] = W83781D_VOLTAGE_TO_REG(2800); /* appears to be a "maximum VCORE" of some kind; mirrors VCORE on the P4 board, but the P3 boards require this to read 2.8V */
|
|
dev->regs[0x03] = 0x60;
|
|
dev->regs[0x04] = dev->regs[0x23]; /* appears to mirror IN3 */
|
|
dev->regs[0x05] = dev->regs[0x22]; /* appears to mirror IN2 */
|
|
dev->regs[0x07] = 0xCD;
|
|
/* 0x08 appears to mirror IN3 Low Limit */
|
|
dev->regs[0x09] = dev->regs[0x0F] = dev->regs[0x11] = 0xF8; /* three instances of */
|
|
dev->regs[0x0A] = dev->regs[0x10] = dev->regs[0x12] = 0xA5; /* the same word */
|
|
dev->regs[0x0B] = 0xAC;
|
|
dev->regs[0x0C] = 0x8C;
|
|
dev->regs[0x0D] = 0x68;
|
|
dev->regs[0x0E] = 0x54;
|
|
|
|
dev->regs[0x53] = dev->regs[0x54] = dev->regs[0x55] = 0xFF;
|
|
dev->regs[0x59] = dev->regs[0x5A] = 0x8F;
|
|
dev->regs[0x5C] = 0xE0;
|
|
dev->regs[0x5D] = 0x48;
|
|
dev->regs[0x5E] = 0xE2;
|
|
dev->regs[0x5F] = 0x3F;
|
|
}
|
|
|
|
/* WARNING: Array elements are register - 0x50. */
|
|
uint16_t temp;
|
|
temp = W83781D_TEMP_TO_REG(dev->values->temperatures[1]);
|
|
dev->regs_bank1[0x0] = temp >> 8;
|
|
dev->regs_bank1[0x1] = temp & 0xFF;
|
|
dev->regs_bank1[0x3] = 0x4B;
|
|
dev->regs_bank1[0x5] = 0x50;
|
|
temp = W83781D_TEMP_TO_REG(dev->values->temperatures[2]);
|
|
dev->regs_bank2[0x0] = temp >> 8;
|
|
dev->regs_bank2[0x1] = temp & 0xFF;
|
|
dev->regs_bank2[0x3] = 0x4B;
|
|
dev->regs_bank2[0x5] = 0x50;
|
|
|
|
w83781d_remap(dev);
|
|
}
|
|
|
|
|
|
static void
|
|
w83781d_close(void *priv)
|
|
{
|
|
w83781d_t *dev = (w83781d_t *) priv;
|
|
|
|
uint16_t isa_io = dev->local & 0xFFFF;
|
|
if (isa_io)
|
|
io_removehandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
|
|
|
|
free(dev);
|
|
}
|
|
|
|
|
|
static void *
|
|
w83781d_init(const device_t *info)
|
|
{
|
|
w83781d_t *dev = (w83781d_t *) malloc(sizeof(w83781d_t));
|
|
memset(dev, 0, sizeof(w83781d_t));
|
|
|
|
dev->local = info->local;
|
|
dev->values = hwm_get_values();
|
|
w83781d_reset(dev, 0);
|
|
|
|
uint16_t isa_io = dev->local & 0xFFFF;
|
|
if (isa_io)
|
|
io_sethandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
|
|
/*
|
|
* Standard Winbond W83781D (or ASUS AS97127F) on ISA and SMBus.
|
|
*/
|
|
const device_t w83781d_device = {
|
|
"Winbond W83781D Hardware Monitor",
|
|
DEVICE_ISA,
|
|
0x295 | W83781D_SMBUS,
|
|
w83781d_init, w83781d_close, NULL,
|
|
NULL, NULL, NULL,
|
|
NULL
|
|
};
|
|
|
|
|
|
/*
|
|
* The ASUS AS99127F is a customized W83781D with no ISA interface (SMBus only),
|
|
* added proprietary registers and different chip/vendor IDs.
|
|
*/
|
|
const device_t as99127f_device = {
|
|
"ASUS AS99127F Rev. 1 Hardware Monitor",
|
|
DEVICE_ISA,
|
|
W83781D_SMBUS | W83781D_AS99127F_REV1,
|
|
w83781d_init, w83781d_close, NULL,
|
|
NULL, NULL, NULL,
|
|
NULL
|
|
};
|
|
|
|
|
|
/*
|
|
* Rev. 2 changes the vendor ID back to Winbond's and brings some other changes.
|
|
*/
|
|
const device_t as99127f_rev2_device = {
|
|
"ASUS AS99127F Rev. 2 Hardware Monitor",
|
|
DEVICE_AT,
|
|
W83781D_SMBUS | W83781D_AS99127F_REV2,
|
|
w83781d_init, w83781d_close, NULL,
|
|
NULL, NULL, NULL,
|
|
NULL
|
|
};
|