791 lines
24 KiB
C
791 lines
24 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the HEADLAND AT286 chipset.
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*
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*
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*
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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* Fred N. van Kempen, <decwiz@yahoo.com>
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* Original by GreatPsycho for PCem.
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2010-2019 Sarah Walker.
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* Copyright 2017-2019 Fred N. van Kempen.
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* Copyright 2017-2019 Miran Grca.
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* Copyright 2017-2019 GreatPsycho.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include "x86.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/device.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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enum {
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HEADLAND_GC103 = 0x00,
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HEADLAND_GC113 = 0x10,
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HEADLAND_HT18_A = 0x11,
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HEADLAND_HT18_B = 0x12,
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HEADLAND_HT18_C = 0x18,
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HEADLAND_HT21_C_D = 0x31,
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HEADLAND_HT21_E = 0x32,
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};
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#define HEADLAND_REV_MASK 0x0F
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#define HEADLAND_HAS_CRI 0x10
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#define HEADLAND_HAS_SLEEP 0x20
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typedef struct headland_mr_t {
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uint8_t valid;
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uint8_t enabled;
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uint16_t mr;
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uint32_t virt_base;
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struct headland_t *headland;
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} headland_mr_t;
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typedef struct headland_t {
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uint8_t revision;
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uint8_t has_cri;
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uint8_t has_sleep;
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uint8_t cri;
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uint8_t cr[7];
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uint8_t indx;
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uint8_t regs[256];
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uint8_t ems_mar;
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headland_mr_t null_mr;
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headland_mr_t ems_mr[64];
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mem_mapping_t low_mapping;
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mem_mapping_t ems_mapping[64];
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mem_mapping_t mid_mapping;
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mem_mapping_t high_mapping;
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mem_mapping_t shadow_mapping[2];
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mem_mapping_t upper_mapping[24];
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} headland_t;
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/* TODO - Headland chipset's memory address mapping emulation isn't fully implemented yet,
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so memory configuration is hardcoded now. */
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static const int mem_conf_cr0[41] = {
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0x00, 0x00, 0x20, 0x40, 0x60, 0xA0, 0x40, 0xE0,
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0xA0, 0xC0, 0xE0, 0xE0, 0xC0, 0xE0, 0xE0, 0xE0,
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0xE0, 0x20, 0x40, 0x40, 0xA0, 0xC0, 0xE0, 0xE0,
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0xC0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
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0x20, 0x40, 0x60, 0x60, 0xC0, 0xE0, 0xE0, 0xE0,
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0xE0
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};
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static const int mem_conf_cr1[41] = {
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0x00, 0x40, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40,
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0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
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0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
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0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
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0x40
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};
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static uint32_t
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get_addr(headland_t *dev, uint32_t addr, headland_mr_t *mr)
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{
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uint32_t bank_base[4];
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uint32_t bank_shift[4];
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uint32_t shift;
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uint32_t other_shift;
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uint32_t bank;
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if ((addr >= 0x0e0000) && (addr <= 0x0fffff))
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return addr;
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else if ((addr >= 0xfe0000) && (addr <= 0xffffff))
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return addr & 0x0fffff;
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if (dev->revision == 8) {
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shift = (dev->cr[0] & 0x80) ? 21 : ((dev->cr[6] & 0x01) ? 23 : 19);
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other_shift = (dev->cr[0] & 0x80) ? ((dev->cr[6] & 0x01) ? 19 : 23) : 21;
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} else {
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shift = (dev->cr[0] & 0x80) ? 21 : 19;
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other_shift = (dev->cr[0] & 0x80) ? 21 : 19;
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}
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/* Bank size = 1 << (bank shift + 2) . */
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bank_shift[0] = bank_shift[1] = shift;
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bank_base[0] = 0x00000000;
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bank_base[1] = bank_base[0] + (1 << shift);
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bank_base[2] = bank_base[1] + (1 << shift);
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if ((dev->revision > 0) && (dev->revision < 8) && (dev->cr[1] & 0x40)) {
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bank_shift[2] = bank_shift[3] = other_shift;
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bank_base[3] = bank_base[2] + (1 << other_shift);
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/* First address after the memory is bank_base[3] + (1 << other_shift) */
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} else {
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bank_shift[2] = bank_shift[3] = shift;
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bank_base[3] = bank_base[2] + (1 << shift);
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/* First address after the memory is bank_base[3] + (1 << shift) */
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}
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if (mr && mr->valid && (dev->cr[0] & 2) && (mr->mr & 0x200)) {
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addr = (addr & 0x3fff) | ((mr->mr & 0x1F) << 14);
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bank = (mr->mr >> 7) & 3;
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if (bank_shift[bank] >= 21)
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addr |= (mr->mr & 0x060) << 14;
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if ((dev->revision == 8) && (bank_shift[bank] == 23))
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addr |= (mr->mr & 0xc00) << 11;
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addr |= bank_base[(mr->mr >> 7) & 3];
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} else if (((mr == NULL) || !mr->valid) && (mem_size >= 1024) && (addr >= 0x100000) && ((dev->cr[0] & 4) == 0))
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addr -= 0x60000;
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return addr;
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}
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static void
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hl_ems_disable(headland_t *dev, uint8_t mar, uint32_t base_addr, uint8_t indx)
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{
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if (base_addr < (mem_size << 10))
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mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + base_addr);
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else
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mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL);
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mem_mapping_disable(&dev->ems_mapping[mar & 0x3f]);
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if (indx < 24) {
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mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_mapping_enable(&dev->upper_mapping[indx]);
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} else
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mem_set_mem_state(base_addr, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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static void
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hl_ems_update(headland_t *dev, uint8_t mar)
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{
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uint32_t base_addr;
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uint32_t virt_addr;
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uint8_t indx = mar & 0x1f;
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base_addr = (indx + 16) << 14;
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if (indx >= 24)
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base_addr += 0x20000;
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hl_ems_disable(dev, mar, base_addr, indx);
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dev->ems_mr[mar & 0x3f].enabled = 0;
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dev->ems_mr[mar & 0x3f].virt_base = base_addr;
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if ((dev->cr[0] & 2) && ((dev->cr[0] & 1) == ((mar & 0x20) >> 5)) && (dev->ems_mr[mar & 0x3f].mr & 0x200)) {
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mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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virt_addr = get_addr(dev, base_addr, &dev->ems_mr[mar & 0x3f]);
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dev->ems_mr[mar & 0x3f].enabled = 1;
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dev->ems_mr[mar & 0x3f].virt_base = virt_addr;
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if (indx < 24)
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mem_mapping_disable(&dev->upper_mapping[indx]);
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if (virt_addr < (mem_size << 10))
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mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + virt_addr);
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else
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mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL);
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mem_mapping_enable(&dev->ems_mapping[mar & 0x3f]);
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}
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flushmmucache();
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}
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static void
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set_global_EMS_state(headland_t *dev, UNUSED(int state))
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{
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for (uint8_t i = 0; i < 32; i++) {
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hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20));
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hl_ems_update(dev, i | ((dev->cr[0] & 0x01) << 5));
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}
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}
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static void
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memmap_state_default(headland_t *dev, uint8_t ht_romcs)
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{
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mem_mapping_disable(&dev->mid_mapping);
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if (ht_romcs)
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mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS);
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else
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mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS);
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mem_mapping_disable(&dev->shadow_mapping[0]);
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mem_mapping_disable(&dev->shadow_mapping[1]);
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}
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static void
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memmap_state_update(headland_t *dev)
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{
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uint32_t addr;
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uint8_t ht_cr0 = dev->cr[0];
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uint8_t ht_romcs = !(dev->cr[4] & 0x01);
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if (dev->revision <= 1)
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ht_romcs = 1;
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if (!(dev->cr[0] & 0x04))
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ht_cr0 &= ~0x18;
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for (uint8_t i = 0; i < 24; i++) {
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addr = get_addr(dev, 0x40000 + (i << 14), NULL);
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mem_mapping_set_exec(&dev->upper_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
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}
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memmap_state_default(dev, ht_romcs);
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if (mem_size > 640) {
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if (ht_cr0 & 0x04) {
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mem_mapping_set_addr(&dev->mid_mapping, 0xA0000, 0x40000);
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mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000);
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mem_mapping_disable(&dev->mid_mapping);
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if (mem_size > 1024) {
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mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_mapping_set_addr(&dev->high_mapping, 0x100000, (mem_size - 1024) << 10);
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mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000);
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}
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} else {
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/* 1 MB - 1 MB + 384k: RAM pointing to A0000-FFFFF
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1 MB + 384k: Any ram pointing 1 MB onwards. */
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/* First, do the addresses above 1 MB. */
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mem_mapping_set_addr(&dev->mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
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mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000);
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if (mem_size > 1024) {
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/* We have ram above 1 MB, we need to relocate that. */
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mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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mem_mapping_set_addr(&dev->high_mapping, 0x160000, (mem_size - 1024) << 10);
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mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000);
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}
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}
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}
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switch (ht_cr0) {
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case 0x18:
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if ((mem_size << 10) > 0xe0000) {
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mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x20000);
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mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000);
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mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x20000);
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mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000);
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} else {
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mem_mapping_disable(&dev->shadow_mapping[0]);
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mem_mapping_disable(&dev->shadow_mapping[1]);
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}
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break;
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case 0x10:
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if ((mem_size << 10) > 0xf0000) {
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mem_set_mem_state(0x0f0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_set_mem_state(0xff0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0f0000, 0x10000);
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mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xf0000);
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mem_mapping_set_addr(&dev->shadow_mapping[1], 0xff0000, 0x10000);
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mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xf0000);
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} else {
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mem_mapping_disable(&dev->shadow_mapping[0]);
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mem_mapping_disable(&dev->shadow_mapping[1]);
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}
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break;
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case 0x08:
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if ((mem_size << 10) > 0xe0000) {
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mem_set_mem_state(0x0e0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_set_mem_state(0xfe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x10000);
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mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000);
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mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x10000);
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mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000);
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} else {
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mem_mapping_disable(&dev->shadow_mapping[0]);
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mem_mapping_disable(&dev->shadow_mapping[1]);
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}
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break;
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case 0x00:
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default:
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mem_mapping_disable(&dev->shadow_mapping[0]);
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mem_mapping_disable(&dev->shadow_mapping[1]);
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break;
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}
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set_global_EMS_state(dev, ht_cr0 & 3);
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}
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static void
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hl_write(uint16_t addr, uint8_t val, void *priv)
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{
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headland_t *dev = (headland_t *) priv;
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switch (addr) {
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case 0x01ec:
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dev->ems_mr[dev->ems_mar & 0x3f].mr = val | 0xff00;
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hl_ems_update(dev, dev->ems_mar & 0x3f);
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if (dev->ems_mar & 0x80)
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dev->ems_mar++;
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break;
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case 0x01ed:
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if (dev->has_cri)
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dev->cri = val;
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break;
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case 0x01ee:
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dev->ems_mar = val;
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break;
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case 0x01ef:
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switch (dev->cri & 0x07) {
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case 0:
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dev->cr[0] = (val & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
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memmap_state_update(dev);
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break;
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case 1:
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dev->cr[1] = (val & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
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memmap_state_update(dev);
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break;
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case 2:
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case 3:
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dev->cr[dev->cri] = val;
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memmap_state_update(dev);
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break;
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case 5:
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if (dev->has_sleep)
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dev->cr[dev->cri] = val;
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else
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dev->cr[dev->cri] = val & 0x0f;
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memmap_state_update(dev);
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break;
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case 4:
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dev->cr[4] = (dev->cr[4] & 0xf0) | (val & 0x0f);
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memmap_state_update(dev);
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break;
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case 6:
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if (dev->revision == 8) {
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dev->cr[dev->cri] = (val & 0xfe) | (mem_size > 8192 ? 1 : 0);
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memmap_state_update(dev);
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}
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static void
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hl_writew(uint16_t addr, uint16_t val, void *priv)
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{
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headland_t *dev = (headland_t *) priv;
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switch (addr) {
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case 0x01ec:
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dev->ems_mr[dev->ems_mar & 0x3f].mr = val;
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hl_ems_update(dev, dev->ems_mar & 0x3f);
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if (dev->ems_mar & 0x80)
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dev->ems_mar++;
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break;
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default:
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break;
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}
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}
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static void
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hl_writel(uint16_t addr, uint32_t val, void *priv)
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{
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hl_writew(addr, val, priv);
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hl_writew(addr + 2, val >> 16, priv);
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}
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static uint8_t
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hl_read(uint16_t addr, void *priv)
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{
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headland_t *dev = (headland_t *) priv;
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uint8_t ret = 0xff;
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switch (addr) {
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case 0x01ec:
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ret = (uint8_t) dev->ems_mr[dev->ems_mar & 0x3f].mr;
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if (dev->ems_mar & 0x80)
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dev->ems_mar++;
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break;
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case 0x01ed:
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if (dev->has_cri)
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ret = dev->cri;
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break;
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case 0x01ee:
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ret = dev->ems_mar;
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break;
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case 0x01ef:
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switch (dev->cri & 0x07) {
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case 0:
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ret = (dev->cr[0] & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
|
|
break;
|
|
|
|
case 1:
|
|
ret = (dev->cr[1] & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
|
|
break;
|
|
|
|
case 6:
|
|
if (dev->revision == 8)
|
|
ret = (dev->cr[6] & 0xfe) | (mem_size > 8192 ? 1 : 0);
|
|
else
|
|
ret = 0;
|
|
break;
|
|
|
|
default:
|
|
ret = dev->cr[dev->cri];
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint16_t
|
|
hl_readw(uint16_t addr, void *priv)
|
|
{
|
|
headland_t *dev = (headland_t *) priv;
|
|
uint16_t ret = 0xffff;
|
|
|
|
switch (addr) {
|
|
case 0x01ec:
|
|
ret = dev->ems_mr[dev->ems_mar & 0x3f].mr | ((dev->cr[4] & 0x80) ? 0xf000 : 0xfc00);
|
|
if (dev->ems_mar & 0x80)
|
|
dev->ems_mar++;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t
|
|
hl_readl(uint16_t addr, void *priv)
|
|
{
|
|
uint32_t ret = 0xffffffff;
|
|
|
|
ret = hl_readw(addr, priv);
|
|
ret |= (hl_readw(addr + 2, priv) << 16);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint8_t
|
|
mem_read_b(uint32_t addr, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
uint8_t ret = 0xff;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
ret = ram[addr];
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint16_t
|
|
mem_read_w(uint32_t addr, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
uint16_t ret = 0xffff;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
ret = *(uint16_t *) &ram[addr];
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t
|
|
mem_read_l(uint32_t addr, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
uint32_t ret = 0xffffffff;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
ret = *(uint32_t *) &ram[addr];
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
mem_write_b(uint32_t addr, uint8_t val, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
ram[addr] = val;
|
|
}
|
|
|
|
static void
|
|
mem_write_w(uint32_t addr, uint16_t val, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
*(uint16_t *) &ram[addr] = val;
|
|
}
|
|
|
|
static void
|
|
mem_write_l(uint32_t addr, uint32_t val, void *priv)
|
|
{
|
|
headland_mr_t *mr = (headland_mr_t *) priv;
|
|
headland_t *dev = mr->headland;
|
|
|
|
addr = get_addr(dev, addr, mr);
|
|
if (addr < (mem_size << 10))
|
|
*(uint32_t *) &ram[addr] = val;
|
|
}
|
|
|
|
static void
|
|
headland_close(void *priv)
|
|
{
|
|
headland_t *dev = (headland_t *) priv;
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
headland_init(const device_t *info)
|
|
{
|
|
headland_t *dev;
|
|
int ht386 = 0;
|
|
|
|
dev = (headland_t *) malloc(sizeof(headland_t));
|
|
memset(dev, 0x00, sizeof(headland_t));
|
|
|
|
dev->has_cri = (info->local & HEADLAND_HAS_CRI);
|
|
dev->has_sleep = (info->local & HEADLAND_HAS_SLEEP);
|
|
dev->revision = info->local & HEADLAND_REV_MASK;
|
|
|
|
if (dev->revision > 0)
|
|
ht386 = 1;
|
|
|
|
dev->cr[0] = 0x04;
|
|
dev->cr[4] = dev->revision << 4;
|
|
|
|
if (ht386)
|
|
device_add(&port_92_inv_device);
|
|
|
|
io_sethandler(0x01ec, 4,
|
|
hl_read, hl_readw, hl_readl, hl_write, hl_writew, hl_writel, dev);
|
|
|
|
dev->null_mr.valid = 0;
|
|
dev->null_mr.mr = 0xff;
|
|
dev->null_mr.headland = dev;
|
|
|
|
for (uint8_t i = 0; i < 64; i++) {
|
|
dev->ems_mr[i].valid = 1;
|
|
dev->ems_mr[i].mr = 0x00;
|
|
dev->ems_mr[i].headland = dev;
|
|
}
|
|
|
|
/* Turn off mem.c mappings. */
|
|
mem_mapping_disable(&ram_low_mapping);
|
|
mem_mapping_disable(&ram_mid_mapping);
|
|
mem_mapping_disable(&ram_high_mapping);
|
|
|
|
mem_mapping_add(&dev->low_mapping, 0, 0x40000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
ram, MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
|
|
if (mem_size > 640) {
|
|
mem_mapping_add(&dev->mid_mapping, 0xa0000, 0x60000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
ram + 0xa0000, MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
mem_mapping_disable(&dev->mid_mapping);
|
|
}
|
|
|
|
if (mem_size > 1024) {
|
|
mem_mapping_add(&dev->high_mapping, 0x100000, ((mem_size - 1024) * 1024),
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
ram + 0x100000, MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
mem_mapping_enable(&dev->high_mapping);
|
|
}
|
|
|
|
for (uint8_t i = 0; i < 24; i++) {
|
|
mem_mapping_add(&dev->upper_mapping[i],
|
|
0x40000 + (i << 14), 0x4000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
mem_size > (256 + (i << 4)) ? (ram + 0x40000 + (i << 14)) : NULL,
|
|
MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
mem_mapping_enable(&dev->upper_mapping[i]);
|
|
}
|
|
|
|
mem_mapping_add(&dev->shadow_mapping[0],
|
|
0xe0000, 0x20000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL,
|
|
MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
mem_mapping_disable(&dev->shadow_mapping[0]);
|
|
|
|
mem_mapping_add(&dev->shadow_mapping[1],
|
|
0xfe0000, 0x20000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL,
|
|
MEM_MAPPING_INTERNAL, &dev->null_mr);
|
|
mem_mapping_disable(&dev->shadow_mapping[1]);
|
|
|
|
for (uint8_t i = 0; i < 64; i++) {
|
|
dev->ems_mr[i].mr = 0x00;
|
|
mem_mapping_add(&dev->ems_mapping[i],
|
|
((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000,
|
|
mem_read_b, mem_read_w, mem_read_l,
|
|
mem_write_b, mem_write_w, mem_write_l,
|
|
ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14),
|
|
MEM_MAPPING_INTERNAL, &dev->ems_mr[i]);
|
|
mem_mapping_disable(&dev->ems_mapping[i]);
|
|
}
|
|
|
|
memmap_state_update(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t headland_gc10x_device = {
|
|
.name = "Headland GC101/102/103",
|
|
.internal_name = "headland_gc10x",
|
|
.flags = 0,
|
|
.local = HEADLAND_GC103,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_gc113_device = {
|
|
.name = "Headland GC101/102/113",
|
|
.internal_name = "headland_gc113",
|
|
.flags = 0,
|
|
.local = HEADLAND_GC113,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_ht18a_device = {
|
|
.name = "Headland HT18 Rev. A",
|
|
.internal_name = "headland_ht18a",
|
|
.flags = 0,
|
|
.local = HEADLAND_HT18_A,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_ht18b_device = {
|
|
.name = "Headland HT18 Rev. B",
|
|
.internal_name = "headland_ht18b",
|
|
.flags = 0,
|
|
.local = HEADLAND_HT18_B,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_ht18c_device = {
|
|
.name = "Headland HT18 Rev. C",
|
|
.internal_name = "headland_ht18c",
|
|
.flags = 0,
|
|
.local = HEADLAND_HT18_C,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_ht21c_d_device = {
|
|
.name = "Headland HT21 Rev. C/D",
|
|
.internal_name = "headland_ht21cd",
|
|
.flags = 0,
|
|
.local = HEADLAND_HT21_C_D,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t headland_ht21e_device = {
|
|
.name = "Headland HT21 Rev. E",
|
|
.internal_name = "headland_ht21",
|
|
.flags = 0,
|
|
.local = HEADLAND_HT21_E,
|
|
.init = headland_init,
|
|
.close = headland_close,
|
|
.reset = NULL,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|