84595f1c78
Unfinished JEGA emulation based on akm's DOSVAX (AX-emulating fork of DOSBox), not yet hooked into the reset of the emulator.
303 lines
7.0 KiB
C
303 lines
7.0 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of the SiS 50x PCI chips.
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*
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* Version: @(#)sis50x.c 1.0.0 2017/05/30
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*
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* Author: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2017-2017 Miran Grca.
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*/
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#include <stdlib.h>
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#include "ibm.h"
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#include "device.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "sis50x.h"
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typedef struct sis501_t
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{
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uint8_t pci_conf[256];
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uint8_t turbo_reg;
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} sis501_t;
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typedef struct sis503_t
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{
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uint8_t pci_conf[256];
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} sis503_t;
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typedef struct sis50x_t
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{
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uint8_t isa_conf[12];
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uint8_t reg;
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} sis50x_t;
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void sis501_recalcmapping(sis501_t *sis501)
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{
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int c, d;
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for (c = 0; c < 1; c++)
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{
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for (d = 0; d < 4; d++)
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{
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// uint32_t base = (((2 - c) << 16) + 0xc0000) + (d << 14);
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uint32_t base = 0xe0000 + (d << 14);
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if (sis501->pci_conf[0x54 + c] & (1 << (d + 4)))
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{
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switch (sis501->pci_conf[0x53] & 0x60)
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{
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case 0x00:
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x20:
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 0x40:
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mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 0x60:
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mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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}
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}
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else
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mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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}
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flushmmucache();
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shadowbios = 1;
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}
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void sis501_write(int func, int addr, uint8_t val, void *p)
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{
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sis501_t *sis501 = (sis501_t *)p;
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//pclog("sis501_write : addr=%02x val=%02x\n", addr, val);
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switch (addr)
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{
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case 0x54: /*Shadow configure*/
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if ((sis501->pci_conf[0x54] & val) ^ 0xf0)
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{
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sis501->pci_conf[0x54] = val;
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sis501_recalcmapping(sis501);
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}
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break;
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}
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if ((addr >= 4 && addr < 8) || addr >= 0x40)
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sis501->pci_conf[addr] = val;
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}
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void sis501_turbo_write(uint16_t port, uint8_t val, void *priv)
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{
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sis501_t *sis501 = (sis501_t *)priv;
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uint8_t valxor = val ^ sis501->turbo_reg;
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sis501->turbo_reg = val;
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if ((val & 4) && (valxor & 4))
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{
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if (sis501->turbo_reg & 2)
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resetpchard();
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else
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softresetx86();
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}
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}
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void sis503_write(int func, int addr, uint8_t val, void *p)
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{
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sis503_t *sis503 = (sis503_t *)p;
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//pclog("sis503_write : addr=%02x val=%02x\n", addr, val);
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if ((addr >= 4 && addr < 8) || addr >= 0x0f)
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sis503->pci_conf[addr] = val;
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}
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void sis50x_write(uint16_t port, uint8_t val, void *priv)
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{
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sis50x_t *sis50x = (sis50x_t *)priv;
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if (port & 1)
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{
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if (sis50x->reg <= 0xB) sis50x->isa_conf[sis50x->reg] = val;
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}
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else
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{
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sis50x->reg = val;
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}
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}
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uint8_t sis501_read(int func, int addr, void *p)
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{
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sis501_t *sis501 = (sis501_t *)p;
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return sis501->pci_conf[addr];
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}
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uint8_t sis501_turbo_read(uint16_t port, void *priv)
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{
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sis501_t *sis501 = (sis501_t *)priv;
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return sis501->turbo_reg;
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}
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uint8_t sis503_read(int func, int addr, void *p)
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{
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sis503_t *sis503 = (sis503_t *)p;
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return sis503->pci_conf[addr];
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}
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uint8_t sis50x_read(uint16_t port, void *priv)
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{
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sis50x_t *sis50x = (sis50x_t *)priv;
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if (port & 1)
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{
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if (sis50x->reg <= 0xB)
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return sis50x->isa_conf[sis50x->reg];
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else
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return 0xff;
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}
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else
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{
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return sis50x->reg;
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}
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}
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void *sis501_init()
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{
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sis501_t *sis501 = malloc(sizeof(sis501_t));
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memset(sis501, 0, sizeof(sis501_t));
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// io_sethandler(0x0cf9, 0x0001, sis501_turbo_read, NULL, NULL, sis501_turbo_write, NULL, NULL, sis501);
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// pci_add_specific(5, sis501_read, sis501_write, sis501);
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pci_add_specific(0, sis501_read, sis501_write, sis501);
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sis501->pci_conf[0x00] = 0x39; /*SiS*/
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sis501->pci_conf[0x01] = 0x10;
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sis501->pci_conf[0x02] = 0x06; /*501/502*/
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sis501->pci_conf[0x03] = 0x04;
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sis501->pci_conf[0x04] = 7;
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sis501->pci_conf[0x05] = 0;
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sis501->pci_conf[0x06] = 0x80;
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sis501->pci_conf[0x07] = 0x02;
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sis501->pci_conf[0x08] = 0; /*Device revision*/
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sis501->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis501->pci_conf[0x0a] = 0x00;
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sis501->pci_conf[0x0b] = 0x06;
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sis501->pci_conf[0x0e] = 0x00; /*Single function device*/
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shadowbios = 1;
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return sis501;
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}
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void *sis503_init()
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{
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sis503_t *sis503 = malloc(sizeof(sis503_t));
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memset(sis503, 0, sizeof(sis503_t));
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// pci_add_specific(6, sis503_read, sis503_write, sis503);
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pci_add_specific(1, sis503_read, sis503_write, sis503);
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sis503->pci_conf[0x00] = 0x39; /*SiS*/
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sis503->pci_conf[0x01] = 0x10;
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sis503->pci_conf[0x02] = 0x08; /*503*/
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sis503->pci_conf[0x03] = 0x00;
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sis503->pci_conf[0x04] = 7;
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sis503->pci_conf[0x05] = 0;
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sis503->pci_conf[0x06] = 0x80;
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sis503->pci_conf[0x07] = 0x02;
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sis503->pci_conf[0x08] = 0; /*Device revision*/
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sis503->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis503->pci_conf[0x0a] = 0x01;
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sis503->pci_conf[0x0b] = 0x06;
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sis503->pci_conf[0x0e] = 0x00; /*Single function device*/
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return sis503;
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}
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void *sis50x_init()
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{
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sis50x_t *sis50x = malloc(sizeof(sis50x_t));
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memset(sis50x, 0, sizeof(sis50x_t));
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io_sethandler(0x22, 0x0002, sis50x_read, NULL, NULL, sis50x_write, NULL, NULL, sis50x);
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}
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void sis501_close(void *p)
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{
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sis501_t *sis501 = (sis501_t *)p;
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free(sis501);
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}
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void sis503_close(void *p)
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{
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sis503_t *sis503 = (sis503_t *)p;
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free(sis503);
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}
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void sis50x_close(void *p)
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{
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sis50x_t *sis50x = (sis50x_t *)p;
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free(sis50x);
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}
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device_t sis501_device =
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{
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"SiS 501/502",
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0,
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sis501_init,
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sis501_close,
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NULL,
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NULL,
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NULL,
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NULL
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};
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device_t sis503_device =
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{
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"SiS 503",
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0,
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sis503_init,
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sis503_close,
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NULL,
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NULL,
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NULL,
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NULL
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};
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device_t sis50x_device =
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{
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"SiS 50x ISA",
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0,
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sis50x_init,
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sis50x_close,
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NULL,
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NULL,
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NULL,
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NULL
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};
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