347 lines
10 KiB
C
347 lines
10 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ACC 2036 chipset.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2025 Miran Grca.
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*/
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#include <inttypes.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/machine.h>
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#include <86box/mem.h>
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#include <86box/port_92.h>
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#include <86box/plat_fallthrough.h>
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#include <86box/plat_unused.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/chipset.h>
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typedef struct {
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uint32_t virt;
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uint32_t phys;
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mem_mapping_t mapping;
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} ram_page_t;
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typedef struct {
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uint8_t reg;
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uint8_t regs[32];
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ram_page_t ram_mid_pages[24];
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ram_page_t ems_pages[4];
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} acc2036_t;
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static uint8_t
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acc2036_mem_read(uint32_t addr, void *priv)
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{
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ram_page_t *dev = (ram_page_t *) priv;
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uint8_t ret = 0xff;
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addr = (addr - dev->virt) + dev->phys;
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if (addr < (mem_size << 10))
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ret = ram[addr];
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return ret;
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}
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static uint16_t
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acc2036_mem_readw(uint32_t addr, void *priv)
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{
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ram_page_t *dev = (ram_page_t *) priv;
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uint16_t ret = 0xffff;
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addr = (addr - dev->virt) + dev->phys;
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if (addr < (mem_size << 10))
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ret = *(uint16_t *) &(ram[addr]);
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return ret;
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}
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static void
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acc2036_mem_write(uint32_t addr, uint8_t val, void *priv)
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{
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ram_page_t *dev = (ram_page_t *) priv;
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addr = (addr - dev->virt) + dev->phys;
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if (addr < (mem_size << 10))
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ram[addr] = val;
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}
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static void
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acc2036_mem_writew(uint32_t addr, uint16_t val, void *priv)
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{
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ram_page_t *dev = (ram_page_t *) priv;
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addr = (addr - dev->virt) + dev->phys;
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if (addr < (mem_size << 10))
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*(uint16_t *) &(ram[addr]) = val;
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}
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static void
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acc2036_recalc(acc2036_t *dev)
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{
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uint32_t ems_bases[4] = { 0x000c0000, 0x000c8000, 0x000d0000, 0x000e0000 };
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int start_i = (ems_bases[dev->regs[0x0c] & 0x03] - 0x000a0000) >> 14;
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int end_i = start_i + 3;
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for (int i = 0; i < 24; i++) {
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ram_page_t *rp = &dev->ram_mid_pages[i];
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mem_mapping_disable(&rp->mapping);
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}
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for (int i = 0; i < 4; i++) {
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ram_page_t *ep = &dev->ems_pages[i];
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mem_mapping_disable(&ep->mapping);
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}
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for (int i = 0; i < 24; i++) {
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ram_page_t *rp = &dev->ram_mid_pages[i];
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if ((dev->regs[0x03] & 0x08) && (i >= start_i) && (i <= end_i)) {
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/* EMS */
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ram_page_t *ep = &dev->ems_pages[i - start_i];
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mem_mapping_disable(&rp->mapping);
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mem_mapping_set_addr(&ep->mapping, ep->virt, 0x000040000);
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mem_mapping_set_exec(&ep->mapping, ram + ep->phys);
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mem_set_mem_state_both(ep->virt, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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} else {
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int master_write;
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int master_read;
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int bit;
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int ew_flag;
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int er_flag;
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int flags;
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uint8_t val;
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mem_mapping_set_addr(&rp->mapping, rp->virt, 0x000040000);
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mem_mapping_set_exec(&rp->mapping, ram + rp->phys);
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if ((i >= 8) && (i <= 15)) {
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/* 0C0000-0DFFFF */
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master_write = dev->regs[0x02] & 0x08;
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master_read = dev->regs[0x02] & 0x04;
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bit = ((i - 8) >> 1);
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val = dev->regs[0x0d] & (1 << bit);
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if (i >= 12) {
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ew_flag = (dev->regs[0x07] & 0x80) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
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er_flag = (dev->regs[0x07] & 0x80) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
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} else {
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ew_flag = (dev->regs[0x07] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
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er_flag = (dev->regs[0x07] & 0x40) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
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}
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flags = (val && master_write) ? MEM_WRITE_INTERNAL : ew_flag;
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flags |= (val && master_read) ? MEM_READ_INTERNAL : er_flag;
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mem_set_mem_state_both(rp->virt, 0x00004000, flags);
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} else if (i > 15) {
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/* 0E0000-0FFFFF */
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master_write = dev->regs[0x02] & 0x02;
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master_read = dev->regs[0x02] & 0x01;
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bit = ((i - 8) >> 2);
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val = dev->regs[0x0c] & (1 << bit);
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if (i >= 20) {
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ew_flag = MEM_WRITE_EXTANY;
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er_flag = MEM_READ_EXTANY;
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} else {
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ew_flag = (dev->regs[0x0c] & 0x10) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
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er_flag = (dev->regs[0x0c] & 0x10) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
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}
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flags = (val && master_write) ? MEM_WRITE_INTERNAL : ew_flag;
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flags |= (val && master_read) ? MEM_READ_INTERNAL : er_flag;
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mem_set_mem_state_both(rp->virt, 0x00004000, flags);
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}
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}
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}
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if (dev->regs[0x00] & 0x40)
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mem_set_mem_state_both(0x00fe0000, 0x00010000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else
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mem_set_mem_state_both(0x00fe0000, 0x00010000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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for (int i = 0x01; i <= 0x06; i++) {
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uint32_t base = 0x00fe0000 - (i * 0x00010000);
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if (dev->regs[i] & 0x40)
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mem_set_mem_state_both(base, 0x00008000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else
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mem_set_mem_state_both(base, 0x00008000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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if (dev->regs[i] & 0x80)
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mem_set_mem_state_both(base + 0x00008000, 0x00008000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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else
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mem_set_mem_state_both(base + 0x00008000, 0x00008000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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}
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mem_remap_top(0);
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if (dev->regs[0x03] & 0x10) {
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if (dev->regs[0x02] & 0x0c)
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mem_remap_top(128);
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else if (dev->regs[0x02] & 0x03)
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mem_remap_top(256);
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else
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mem_remap_top(384);
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}
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flushmmucache_nopc();
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}
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static uint8_t
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acc2036_in(uint16_t port, void *priv) {
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acc2036_t *dev = (acc2036_t *) priv;
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uint8_t reg = dev->reg - 0x20;
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uint8_t ret = 0xff;
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if (port & 0x0001) switch (dev->reg) {
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default:
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break;
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case 0x20 ... 0x2e:
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case 0x31 ... 0x3f:
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ret = dev->regs[reg];
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break;
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} else
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ret = dev->reg;
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return ret;
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}
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static void
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acc2036_out(uint16_t port, uint8_t val, void *priv) {
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acc2036_t *dev = (acc2036_t *) priv;
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uint8_t reg = dev->reg - 0x20;
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if (port & 0x0001) switch (dev->reg) {
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default:
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break;
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case 0x20 ... 0x23:
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dev->regs[reg] = val;
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acc2036_recalc(dev);
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break;
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case 0x24 ... 0x2b:
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dev->regs[reg] = val;
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dev->ems_pages[(reg - 0x04) >> 1].phys = ((dev->regs[reg & 0xfe] & 0x1f) << 19) |
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((dev->regs[reg | 0x01] & 0x1f) << 14);
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acc2036_recalc(dev);
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break;
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case 0x2c: case 0x2d:
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dev->regs[reg] = val;
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acc2036_recalc(dev);
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break;
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case 0x2e:
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dev->regs[reg] = val | 0x10;
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break;
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case 0x31:
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dev->regs[reg] = val;
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mem_a20_alt = (val & 0x01);
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mem_a20_recalc();
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flushmmucache();
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if (val & 0x02) {
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softresetx86(); /* Pulse reset! */
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cpu_set_edx();
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flushmmucache();
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}
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break;
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case 0x32 ... 0x3f:
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dev->regs[reg] = val;
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break;
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} else
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dev->reg = val;
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}
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static void
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acc2036_close(void *priv)
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{
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acc2036_t *dev = (acc2036_t *) priv;
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free(dev);
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}
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static void *
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acc2036_init(UNUSED(const device_t *info))
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{
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acc2036_t *dev = (acc2036_t *) calloc(1, sizeof(acc2036_t));
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for (int i = 0; i < 24; i++) {
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ram_page_t *rp = &dev->ram_mid_pages[i];
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rp->virt = 0x000a0000 + (i << 14);
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rp->phys = 0x000a0000 + (i << 14);
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mem_mapping_add(&rp->mapping, rp->virt, 0x00004000,
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acc2036_mem_read, acc2036_mem_readw, NULL,
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acc2036_mem_write, acc2036_mem_writew, NULL,
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ram + rp->phys, MEM_MAPPING_INTERNAL, rp);
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}
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for (int i = 0; i < 4; i++) {
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ram_page_t *ep = &dev->ems_pages[i];
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ep->virt = 0x000d0000 + (i << 14);
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ep->phys = 0x00000000 + (i << 14);
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mem_mapping_add(&ep->mapping, ep->virt, 0x00004000,
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acc2036_mem_read, acc2036_mem_readw, NULL,
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acc2036_mem_write, acc2036_mem_writew, NULL,
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ram + ep->phys, MEM_MAPPING_INTERNAL, ep);
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mem_mapping_disable(&ep->mapping);
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}
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mem_mapping_disable(&ram_mid_mapping);
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dev->regs[0x00] = 0x02;
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dev->regs[0x0e] = 0x10;
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dev->regs[0x11] = 0x01;
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dev->regs[0x13] = 0x40;
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dev->regs[0x15] = 0x40;
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dev->regs[0x17] = 0x40;
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dev->regs[0x19] = 0x40;
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dev->regs[0x1b] = 0x40;
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dev->regs[0x1c] = 0x22;
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dev->regs[0x1d] = 0xc4;
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dev->regs[0x1f] = 0x30;
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acc2036_recalc(dev);
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mem_a20_alt = 0x01;
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mem_a20_recalc();
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flushmmucache();
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io_sethandler(0x00f2, 0x0002,
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acc2036_in, NULL, NULL, acc2036_out, NULL, NULL, dev);
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device_add(&port_92_device);
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return dev;
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}
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const device_t acc2036_device = {
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.name = "ACC 2036",
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.internal_name = "acc2036",
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.flags = 0,
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.local = 0,
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.init = acc2036_init,
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.close = acc2036_close,
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.reset = NULL,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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